參數(shù)資料
型號: MC68HC908RK2DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 152/158頁
文件大?。?/td> 1020K
代理商: MC68HC908RK2DW
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
93
Chapter 8
Low-Voltage Inhibit (LVI)
8.1 Introduction
The low-voltage inhibit (LVI) module monitors the voltage on the VDD pin and will set a low voltage sense
bit when VDD voltage falls to the LVI sense voltage. The LVI will force a reset when the VDD voltage falls
to the LVI trip voltage.
8.2 Features
Features of the LVI module include:
Detects two levels of low-voltage condition:
Low-voltage detection
Low-voltage reset
User-configurable for stop mode
8.3 Functional Description
Figure 8-1 shows the structure of the LVI module. The LVI module contains a bandgap reference circuit
and two comparators. The LVI monitors VDD voltage during normal MCU operation. When enabled, the
LVI module generates a reset when VDD falls below the VLVR threshold.
Figure 8-1. LVI Module Block Diagram
In addition to forcing a reset condition, the LVI module has a second circuit dedicated to low-voltage
detection. When VDD falls below VLVS, the output of the low-voltage comparator asserts the LOWV flag
in the LVI status register (LVISR). In applications that require detecting low batteries, software can
monitor by polling the LOWV bit.
DEAD
DETECTOR
STOP INSTRUCTION
VDD > VLVR = 0
VDD VLVR = 1
VDD
RESET
BATTERY
WEAK
DETECTOR
BATTERY
LOWV
VDD > VLVS = 0
VDD ≤ VLVS = 1
LOWV FLAG
V
DD
DIGITAL FILTER
CGMXCLK
LVI STOP BIT IN CONFIGURATION REGISTER
LVI PWR BIT IN CONFIGURATION REGISTER
LVIRST BIT IN CONFIGURATION REGISTER
LVITRIP
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