參數(shù)資料
型號(hào)： MC68HC908RK2DW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝： PLASTIC, SOIC-20
文件頁數(shù)： 47/158頁
文件大?。?/td> 1020K
代理商： MC68HC908RK2DW
Development Support
MC68HC908RK2 Data Sheet, Rev. 5.1
140
Freescale Semiconductor
12.3.1.1 Monitor Mode Entry
Table 12-1 shows the pin conditions for entering monitor mode.
Enter monitor mode by either:
Executing a software interrupt instruction (SWI), or
Applying a logic 0 and then a logic 1 to the RST pin
NOTE
Upon entering monitor mode, an interrupt stack frame plus a stacked H
register will leave the stack pointer at address $00F9.
Once out of reset, the MCU waits for the host to send eight security bytes (see 12.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host computer, indicating that it
is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the
$FE page instead of the $FF page and allow code execution from the internal monitor firmware instead
of user code. The COP module is disabled in monitor mode as long as VTST (see Chapter 13 Electrical
Specifications is applied to either the IRQ pin or the RST pin. (See Chapter 10 System Integration Module
(SIM) for more information on modes of operation.) The ICG module is bypassed in monitor mode as long
as VTST is applied to the IRQ pin. RST does not affect the ICG.
Table 12-2 is a summary of the differences between user mode and monitor mode.
Table 12-1. Monitor Mode Entry
IRQ
Pin
PTB0
Pin
PTB2
Pin
PTA0
Pin
CGMOUNT(1)
1. If the high voltage (VTST) is removed from the IRQ pin while in monitor mode, the clock
select bit (CS) controls the source of CGMOUT.
Bus
Frequency
VTST
(2)
101
Table 12-2. Mode Differences
Modes
Functions
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
1. If the high voltage (VTST) is removed from the IRQ pin while in monitor mode, the SIM asserts
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the
configuration register. See 13.6 3.0-Volt DC Electrical Characteristics.
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
CGMXCLK
2
-----------------------------
CGMOUT
2
--------------------------
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