參數(shù)資料
型號: MC68HC908RK2DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 48/158頁
文件大?。?/td> 1020K
代理商: MC68HC908RK2DW
Monitor Module
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
141
12.3.1.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
The data transmit and receive rate is determined by the crystal. Transmit and receive baud rates must be
identical.
Figure 12-6. Monitor Data Format
Figure 12-7. Sample Monitor Waveforms
12.3.1.3 Echoing
As shown in Figure 12-8, the monitor ROM immediately echoes each received byte back to the PTA0 pin
for error checking.
Any result of a command appears after the echo of the last byte of the command.
Figure 12-8. Read Transaction
12.3.1.4 Break Signal
A start bit followed by nine low bits is a break signal. (See Figure 12-9.) When the monitor receives a break
signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
BIT 5
START
BIT
BIT 0
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2
BIT 3
BIT 4
BIT 6
BIT 7
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
1, 2, 3
BIT 5
START
BIT
BIT 0
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2
BIT 3
BIT 4
BIT 6
BIT 7
START
BIT
BIT 0
BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2
$A5
BREAK
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
1, 2, 3
ADDR. HIGH
READ
ADDR. HIGH
ADDR. LOW
DATA
ECHO
SENT TO
MONITOR
RESULT
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
1
3
1
3
1
2
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