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參數(shù)資料
| 型號： | MC68HC908RK2DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 119/158頁 |
| 文件大?。?/td> | 1020K |
| 代理商： | MC68HC908RK2DW |
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Functional Description
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
63
6.3.2.2 Modulo N Divider
The modulo N divider creates the low-frequency base clock (IBASE) by dividing the internal clock (ICLK)
by the ICG multiplier factor (N) contained in the ICG multiplier register (ICGMR). When N is programmed
to a $01 or $00, the divider is disabled and ICLK is passed through to IBASE undivided. When the internal
clock generator is stable, the frequency of IBASE will be equal to the nominal frequency (fNOM) of
307.2 kHz
±25%.
6.3.2.3 Frequency Comparator
The frequency comparator effectively compares the low-frequency base clock (IBASE) to a nominal
frequency, fNOM. First, the frequency comparator converts IBASE to a voltage by charging a known
capacitor with a current reference for a period dependent on IBASE. This voltage is compared to a voltage
reference with comparators, whose outputs are fed to the digital loop filter. The dependence of these
outputs on the capacitor size, current reference, and voltage reference causes up to
±25 percent error in
fNOM.
6.3.2.4 Digital Loop Filter
The digital loop filter (DLF) uses the outputs of the frequency comparator to adjust the internal clock
(ICLK) clock period. The DLF generates the DCO divider control bits (DDIV[3:0]) and the DCO stage
control bits (DSTG[7:0]), which are fed to the DCO. The DLF first concatenates the DDIV and DSTG
registers (DDIV[3:0]:DSTG[7:0]) and then adds or subtracts a value dependent on the relative error in the
low-frequency base clock’s period, as shown in Table 6-1. In some extreme error conditions, such as
operating at a VDD level which is out of specification, the DLF may attempt to use a value above the
maximum ($9FF) or below the minimum ($000). In both cases, the value for DDIV will be between $A and
$F. In this range, the DDIV value will be interpreted the same as $9 (the slowest condition). Recovering
from this condition requires subtracting (increasing frequency) in the normal fashion until the value is
again below $9FF (if the desired value is $9xx, the value may settle at $Axx through $Fxx, an acceptable
operating condition). If the error is less than
±5%, the internal clock generator’s filter stable indicator
(FICGS) is set, indicating relative frequency accuracy to the clock monitor.
Table 6-1. Correction Sizes from DLF to DCO
Frequency Error
of IBASE Compared
to fNOM
DDVI[3:0]:
DSTG[7:0]
Correction
Current to New
DDIV[3:0]:DSTG[7:0]
Relative Correction
in DCO
IBASE < 0.85 fNOM
–32 (–$020)
Min
$xFF to $xDF
–2/31
–6.45%
Max
$x20 to $x00
–2/19
–10.5%
0.85 fNOM < IBASE
IBASE < 0.95 fNOM
–8 (–$008)
Min
$xFF to $xF7
–0.5/31
–1.61%
Max
$x08 to $x00
–0.5/17.5
–2.86%
0.95 fNOM < IBASE
IBASE < fNOM
–1 (–$001)
Min
$xFF to $xFE
–0.0625/31
–0.202%
Max
$x01 to $x00
–0.0625/17.0625
–0.366%
fNOM < IBASE
IBASE < 1.05 fNOM
+1 (+$001)
Min
$xFE to $xFF
+0.0625/30.9375
+0.202%
Max
$x00 to $x01
+0.0625/17
+0.368%
1.05 fNOM < IBASE
IBASE < 1.15 fNOM
+8 (+$008)
Min
$xF7 to $xFF
+0.5/30.5
+1.64%
Max
$x00 to $x08
+0.5/17
+2.94%
1.15 fNOM < IBASE
+32 (+$020)
Min
$xDF to $xFF
+2/29
+6.90%
Max
$x00 to $x20
+2/17
+11.8%
x: Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when
an addition to DSTG[7:0] carries or borrows.
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