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CHAPTER 4 CLOCKS
4.1
Clocks
The clock generation block controls the operating clock of the CPU and peripheral
functions (resources). The following four clocks are available:
Oscillation clock
Main clock
PLL clock
Machine clock
s Clocks
The clock generation block contains the oscillation circuit and the PLL clock multiplier circuit.
The clock generation block controls the oscillation stabilization wait interval and PLL clock
multiplication as well as controls the operation of switching the clock with a clock selector.
r Oscillation clock frequency (HCLK)
The oscillation clock is generated either from an oscillator connected to the X0 and X1 pins or
by input of an external clock.
r Main clock
The main clock, which is the oscillation clock divided by 2, supplies the clock input to the
timebase timer and the clock selector.
r PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock in the internal PLL clock multiplier
circuit. Four different clocks (multiplied by 1 through 4) can be generated.
r Machine clock
The machine clock is the operating clock of the CPU and peripheral functions (resources). One
machine clock cycle is called a machine cycle. Either the main clock or a PLL clock can be
selected.
Note:
If the operating voltage is 5 V, an oscillation clock frequency from 3 MHz to 16 MHz can be
used. The maximum operating frequency of the CPU and peripheral functions (resources) is
16 MHz. If a frequency multiplier higher than the operating frequency is specified, devices
will not operate normally. If the oscillation clock of 16MHz is generated, only a multiplier of 1
can be specified.