
490
CHAPTER 20 1M-BIT (128KB) FLASH MEMORY
[Bit 5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is 1, writing after the command sequence (see Section
20.4 "Starting the Flash
Memory Automatic Algorithm") is issued to the FC to FF bank writes to the flash memory
area. When this bit is 0, the write/erase signal is not generated. This bit is used when the
flash memory write/erase command is started.
If write/erase is not performed, it is recommended that this bit be set to 0 to prevent data
from being mistakenly written to the flash memory.
0: Disables flash memory write/erase.
1: Enables flash memory write/erase.
[Bit 4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is 0. However, Suspend commands,
such as the Read/Reset command and Sector Erase Suspend command, can be accepted
even if this bit is 0.
0: Write/erase is being executed.
1: Write/erase has terminated (next data write/erase enabled).
[Bit 3] Reserved bit
These bits are reserved for testing. During regular use, they should always be set to 0.
[Bits 2 and 1] Free bits
During regular use, they should always be set to 0.
[Bit 0] LPM (low power mode)
Setting LPM bit to "1" minimizes the select signal to flash memory when flash memory is
accessed, thereby suppressing the power consumption of the main unit of flash memory.
However, because the access time when this bit is 1 is considerably longer than the access
time when this bit is 0, flash memory access is impossible when the CPU operates at high
speed. Operate the CPU at a frequency of 4 MHz or lower when using this mode.
0: Normal power consumption mode
1: Low-power consumption mode (The CPU operates at an internal operating frequency of
4 MHz or lower.)
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that
decisions are made using one or the other of these bits.
1 machine cycle
Automatic algorithm
Termination timing
RDYINT bit
RDY bit