
263
12.1 Overview of Multifunctional Timers
r Input capture (four channels)
The input capture unit consists of input capture data registers (IPCP0 to IPCP3) corresponding
to the external input pins (IN0 to IN3) and input capture control registers (ICS01 and ICS23).
When a valid edge of the signal that is input through an external input pin is detected, the
counter value of the 16-bit free-running timer can be stored in an input capture data register
(IPCP0 to IPCP3) and, at the same time, an interrupt can be output.
Each channel of the input capture unit can be operated independently.
A valid edge (rising edge, falling edge, and both edges) of the external signal can be set.
An interrupt can be output by detecting a valid edge of an external signal (ICS01, ICS23:
ICE0="1", ICE1="1", ICE2="1", ICE3="1").
r 8/16-bit PPG timer (8-bit: six channels, 16-bit: three channels)
The 8/16-bit PPG timer consists of an 8-bit down-counter (PCNT), PPG control registers
(PPGC0 to PPGC5), PPG clock control registers (PCS01, PCS23, PCS45), and PPG reload
registers (PRLL0 to PRLL5, PRLH0 to PRLH5).
The 8/16-bit PPG timer works as an event timer when it is used as an 8/16-bit reload timer. It is
also possible to output pulses of any frequency and duty ratio.
8-bit PPG mode
Each channel operates independently as an 8-bit PPG.
8-bit prescaler + 8-bit PPG mode
8-bit PPG operation at any frequency is enabled by operating channel 0 (channel 2,
channel 4) as an 8-bit prescaler and counting channel 1 (channel 3, channel 5) using the
underflow output of channel 0 (channel 2, channel 4).
16-bit PPG mode
16-bit PPG operation is enabled by linking channel 0 (channel 2, channel 4) and channel
1 (channel 3, channel 5).
PPG operation
Pulse waveforms can be output at any frequency and duty ratio (ratio of the "H" level
period to the "L" level period of pulse waveforms). The timer can also be used as a D/A
converter by using an external circuit.
r Waveform generator
The waveform generation block consists of an 8-bit timer, 8-bit timer control registers (DTCR0 to
DTCR2), 8-bit reload registers (TMRR0 to TMRR2), and a waveform control register (SIGCR).
This circuit can generate DC chopper output and the non-overlap 3-phase waveform output
used for converter control by using the real-time output (RT0 to RT5) and the 8/16-bit PPG
timer.
By using the 8-bit timer as a dead-time timer, non-overlap waveforms can be generated by
adding non-overlap time delays to the pulse output of the PPG timer (dead-time timer
function).
By using the 8-bit timer as a dead-time timer, non-overlap waveforms can be generated by
adding non-overlap time delays to the real-time output (RT1, RT3, RT5) of the PPG timer
(dead-time timer function).
The GATE signal can be generated and the PPG timer operation can be controlled by
matching (rising edge of the real-time output (RT)) of the counter value of 16-bit free-running
timer and a compare register (OCCP0 to OCCP5) value of the output compare (GATE
function).