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型號(hào)：	MB90V560CR
廠商：	FUJITSU LTD
元件分類(lèi)：	微控制器/微處理器
英文描述：	16-BIT, 8 MHz, MICROCONTROLLER, CPGA256
封裝：	PGA-256
文件頁(yè)數(shù)：	54/616頁(yè)
文件大?。?/td>	15240K
代理商：	MB90V560CR

6.4 Hardware Interrupts

s Hardware Interrupt Operation

Figure 6.4-2 Hardware Interrupt Operation

1. An interrupt cause is output within the peripheral functions (resources).

2. If the interrupt enable bit in the peripheral functions (resources) is set to enable interrupts,

interrupt requests are output from the peripheral functions (resources) to the interrupt

3. The interrupt controller that receives interrupt requests from the peripheral functions

(resources) checks the priorities of interrupt requests simultaneously received and transfers

the interrupt level (IL) of an interrupt request with the highest priority to the CPU.

4. The CPU compares the interrupt level (IL) requested by the interrupt controller with the

interrupt level mask register (ILM).

5. If the comparison indicates a higher priority than the current interrupt processing level, the

CPU checks the contents of the I flag in the condition code register (CCR).

6. If, in the check, the I flag in the CCR is found to be set to Enabled (CCR: I = "1"), the CPU

waits until the execution of an instruction being executed is terminated.

terminated, the CPU sets the requested level (IL2 to IL0) in the ILM.

7. The values in the dedicated registers are saved to the system stack.

The processing

branches to the interrupt processing routine.

8. If a program in the interrupt processing routine sets the interrupt request flag bit of a

peripheral function (resource) to "0" and the RETI instruction is executed, data saved on the

system stack is restored to the dedicated registers and the interrupt processing is

F2MC-16LX CPU

Other peripheral functions

Peripheral function that generated the

interrupt request

Interrupt controller

PS : Processor status

I: Interrupt enable flag

ILM : Interrupt level mask register

: Instruction register

: Interrupt level setting bit in the interrupt control register (ICR)

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