
341
13.4 UART Registers
s Output Data Register (SODR0/SODR1)
Figure 13.4-6 Output Data Register (SODR0/SODR1)
When data to be transmitted is written to the output data register (SODR0/SODR1), if
transmission is enabled, the send data is transferred to the transmission shift register, converted
into serial data, and then transmitted from the serial data output pin (SOT0/SOT1 pin). When
the data length is 7 bits long in operation mode 0, bit7 (D7) becomes invalid.
When the transmission data is written to the output data register, the transmission data empty
flag bit (TDRE) of the status register (SSR0/SSR1) is cleared to "0".
When transfer to the
transmission shift register is completed, the status register is set to "1". If the transmission data
empty flag bit (TDRE) is "1", the next send data can be written. When the transmission data
empty flag bit (TDRE) is set to "1" while the transmission interrupt request output is enabled
(SSR0/SSR1: TIE="1"), a transmission interrupt is output.
When a transmission interrupt is
output, write the next transmission data after the transmission data empty flag bit (TDRE) is set
to "1".
Note:
The output data register (SODR0/SODR1) is a write-only register and the input data register
(SIDR0/SIDR1) is a read-only register. These registers are located at the same address,
and so the read value is different from the write value. Therefore, instructions that perform a
read-modify-write (RMW) operation such as the INC/DEC instruction cannot be used.
D3
D0
D1
D2
D7
D4
D5
D6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
XXXXXXXXB
ch0:000022 H
ch1:000026 H
Address
Initial value
W : Write only
X : Indefinite
W