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11.4 16-Bit Reload Timer Registers
11.4.2 Timer Control Ctatus Register, Low Part (TMCSR0/
TMCSR1: L)
The lower seven bits of the timer control status registers (TMCSR0 and TMCSR1) set
the operating conditions for the 16-bit reload timer, enable and disable counting,
control interrupts, and check the statuses of interrupt requests.
s Timer Control Status Register, Low Part (TMCSR0/TMCSR1: L)
Figure 11.4-3 Timer Control Status Register, Low Part (TMCSR0/TMCSR1: L)
RELD INTE
CNTE TRG
UF
*
MOD0 OUTE OUTL
R/W
R/W R/W R/W R/W R/W R/W
TRG
0
1
Software trigger bit
OUTL
Pin output level selection bit
Square wave of H during counting
Square wave of L during counting
Toggle output of L when counting is started.
Toggle output of H when counting is started.
In single-shot mode
(RELD="0")
UF
Underflow interrupt request flag bit
No interrupt request issued
Interrupt request issued
Clearing the interrupt request
No effect on operation
During reading
In reload mode
(RELD="1")
During writing
Timer output enable bit
Registers and pins corresponding to each channel
I/O port
Timer output
No change, no effect on other bits
Counting starts after data loading
CNTE
0
1
Count enable bit
Counting stopped
Counting enabled (wait for the start trigger))
INTE
0
1
0
1
Underflow interrupt request enable bit
Interrupt request output disabled
Interrupt request output enabled
RELD
0
1
0
1
Reload selection bit
One-shot mode (reload disabled)
Reload mode (reload enabled)
P21
TO0
OUTE
0
1
Pin functions
TMCSR0
P23
TO1
TMCSR1
R/W : Read/write
: Initial value
*
: See Section 11.4.1, "Timer control status register, high part (TMCSR0, TMCSR1: H)," for MOD0 (bit 7)
Address
Initial value
bit6
bit7
bit5
bit4
bit3
bit2
bit1
bit0
00000000 B
ch0:000082H
ch1:000086H