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10.4 Operation of the Watchdog Timer
The watchdog timer generates a watchdog reset by an overflow of the watchdog
counter.
s Watchdog Timer Operation
Operation of the watchdog timer requires the setting in
Figure 10.4-1 "Setting of the Watchdog
Timer".
Figure 10.4-1 Setting of the Watchdog Timer
r Activating the watchdog timer
To activate the watchdog timer, set the watchdog control bit (WTE) of the watchdog timer
control register (WDTC) to "0" for the first time after a reset from the watchdog timer is
generated after a power-on reset. The interval can be set in the interval setting bits (WT1,
WT0) of the watchdog timer control register (WDTC).
The watchdog timer, after being activated, can be stopped using a power-on reset or a reset
from the watchdog timer. The watchdog timer cannot be stopped by an external reset, a
software reset, writing to the watchdog control bit (WTE) of the watchdog timer control
register (WDTC), or transition to sleep or timebase timer mode.
r Clearing the watchdog timer
To clear the watchdog timer, set the watchdog control bit (WTE) of the watchdog timer
control register (WDTC) to "0".
The watchdog timer can be cleared also by input of an external reset or an internal reset or
transition to sleep mode.
Transition to timebase timer mode clears and stops the watchdog timer.
r Intervals for the watchdog timer
Figure 10.4-2 "Clear Timing and Watchdog Timer Intervals" shows the relationship between the
clear timing of the watchdog timer and intervals.
r Checking a reset cause
A reset cause can be determined by checking the PONR, WRST, ERST, and SRST bits of the
watchdog timer control register (WDTC) after a reset.
0
: Used
0
: Set 0.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PONR
WRST ERST SRST WTE WT1 WT0
Address
0000A8H