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11.1 Overview of the 16-Bit Reload Timer
s Event Count Mode (External Clock Mode)
The 16-bit reload timer is in event count mode (external clock) if the count clock setting bits
(CSL1, SCL0) of the timer control status register (TMCSR) are set to "11B". Counting starts
when a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode
setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the CNTE bit is set to "1".
The 16-bit reload timer can also be used as an interval timer if external clock is input
periodically.
s Counter Operation
r Reload mode
Counting starts when an underflow of the 16-bit down counter (change from "0000H" to
"FFFFH") loads the values of the 16-bit reload register (TMRLR0/TMRHR0, TMRLR1/TMRHR1)
into the 16-bit down counter. Since the 16-bit reload timer causes an interrupt request to occur
for an underflow condition, it can be used as an interval timer. Every time an underflow occurs,
a reversed toggle waveform can be output from the T0 pin.
r Single-shot mode
An underflow of the 16-bit down counter (change from "0000H" to "FFFFH") stops counting.
Reference:
16-bit reload timer 0 can be used to create the baud rate of UART0.
16-bit reload timer 1 can be used to create the baud rate of UART1 and provide a start
trigger of the A/D converter.
Table 11.1-2 Intervals for the 16-Bit Reload Timer
Count clock
Count clock period
Interval
Internal clock
21
/φ (0.125 s)
0.125
s to 8.192 ms
23
/φ (0.5 s)
0.5
s to 32.768 ms
25
/φ (2.0 s)
2.0
s to 131.1 ms
External clock
23
/φ or more (0.5 s)
0.5
s or more
φ : Mchine clock
Values in parentheses are for a 16 MHz machine clock.