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型號(hào)：	MB90V560CR
廠商：	FUJITSU LTD
元件分類(lèi)：	微控制器/微處理器
英文描述：	16-BIT, 8 MHz, MICROCONTROLLER, CPGA256
封裝：	PGA-256
文件頁(yè)數(shù)：	260/616頁(yè)
文件大小：	15240K
代理商：	MB90V560CR

CHAPTER 12 MULTIFUNCTIONAL TIMERS

s Generating Non-Overlap Waveforms of PPG Timer (PPG1, PPG3, PPG5)

Non-overlap waveforms with positive-polarity waveform output (DTCR: DMOD="0") are

generated by applying a delay of the non-overlap time specified in the 8-bit reload register

(TMRR) at a rising edge of the PPG timer (PPG1, PPG3, PPG5) pulses and PPG timer

(PPG1, PPG3, PPG5) inverted pulses. If the pulse width of the PPG timer (PPG1, PPG3,

PPG5) is smaller than the specified non-overlap time, the 8-bit timer restarts counting from

"00H" at the next PPG timer pulse edge.

[Register settings]

Figure 12.4-19 Generation of Positive-Polarity Non-Overlap Waveforms of PPG Timer

Non-overlap waveforms with negative-polarity waveform output (DTCR: DMOD="1") are

generated by applying a delay of the non-overlap time specified in the 8-bit reload register

(TMRR) at a falling edge of the PPG timer (PPG1, PPG3, PPG5) inverted pulses and PPG

timer (PPG1, PPG3, PPG5) pulses.

If the pulse width of the PPG timer (PPG1, PPG3,

PPG5) is smaller than the specified non-overlap time, the 8-bit timer restarts counting from

TCDT: 0000000000000000B

CPCLR: XXXXXXXXXXXXXXXXB (Cycle setting)

TCCS: X--XXXXXXX0X0XXXB

OCS: ----1XXXXXXXX--11B

OCCP: XXXXXXXXXXXXXXXXB (Compare value setting)

DTCR: 01000111B

TMRR: XXXXXXXXB (Non-overlap time setting)

SIGCR: XXXXXXXXB (DTTI input and 8-bit timer operating clock settings)

Set X according to user’s operation.

-: Undefined bit

One machine cycle

Output signal

Waveform with a delay applied at a rising edge of PPG1

Waveform with a delay applied at a rising edge of PPG3

Waveform with a delay applied at a rising edge of PPG5

Waveform with a delay applied at a rising edge of PPG1 inverted pulses

Waveform with a delay applied at a rising edge of PPG3 inverted pulses

Waveform with a delay applied at a rising edge of PPG5 inverted pulses

Set value of

TMRR register

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