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5.8 Usage Notes on Low Power Consumption Mode
5.8
Usage Notes on Low Power Consumption Mode
Note the following items when using low power consumption mode:
Switching to standby mode and interrupts
Release of standby mode by an interrupt
Release of stop mode by an external interrupt
Oscillation stabilization wait interval
s Switching to Standby Mode and Interrupts
While an interrupt request is output, the microcontroller does not enter standby mode even if the
stop mode bit (STP) of the low power consumption mode control register (LPMCR) is set to "1",
the sleep mode bit (SLP) is set to "1", or the timebase timer mode bit (TMD) is set to "0".
s Release of Standby Mode by an Interrupt
Standby mode is released if an interrupt request with an interrupt level higher than 7 (Interrupt
control register ICR: IL2, IL1, IL0 = "000B" to "110B") is output in sleep mode, timebase timer
mode, or stop mode.
If the interrupt level setting bit (ICR: IL2, IL1, IL0) corresponding to an interrupt request has a
priority higher than the interrupt level mask register (ILM) and the interrupt enable flag of the
condition code register is enabled (CCR:I = 1), the interrupt is accepted and the interrupt
processing routine is executed. Unless the interrupt is accepted, the processing starts again
from the next instruction to the one that set standby mode.
Note:
Interrupt disable setting is required before the setting of standby mode unless an interrupt
processing routine is executed immediately after standby mode is released.
s Release of Stop Mode by an External interrupt
To release stop mode by an external interrupt, set the DTP/interrupt enable register (ENIR) and
the request level setting register (ELVR) before the microcontroller enters stop mode.
Select one of the "H" level, "L" level, rising edge, and falling edge as an input cause.