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9.3 Timebase Timer Control Register (TBTC)
Table 9.3-1 Function Description of Each Bit in the Timebase Timer Control Register (TBTC)
Bit name
Function
bit15
RESV:
Reserved bit
Be sure to write 1 to this bit.
bit14
bit13
Not used
When read, the value is undefined.
Writing has no effect on operation.
bit12
TBIE:
Interrupt request
enable bit
This bit enables interrupt requests.
When this bit and the interrupt request flag bit (TBOF) are 1, an interrupt
request is output.
bit11
TBOF:
Interrupt request flag
bit
TBOF is a flag bit for an interrupt request.
This bit is set to "1" when the interval timer bit selected for the timebase
timer counter overflows.
When the interrupt request enable bit (TBIE) is set to "1", an interrupt
request is output.
Set this bit to "0" to clear an interrupt request.
When this bit is set to "1", there is no effect on operation.
Note:Note:
To set this bit to "0", set the interrupt request enable bit (TBIE) or the
interrupt level mask register (ILM) of the processor status (PS) to
Disabled.
This bit is cleared to "0" when a transition to stop mode occurs, the
timebase timer is cleared due to the timebase timer initialization bit
(TBR), or a reset occurs.
bit10
TBR:
Timebase timer
initialization bit
Used to clear the timebase timer counter.
When 0 is written to this bit, the counter is cleared and the TBOF bit is
cleared. If 1 is written, the bit does not change and there is no effect.
[Reference]
The read value is always 1.
bit9
bit8
TBC1, TBC0:
Interval selection bit
Used to select an interval timer cycle.
The bit for the interval timer of the timebase timer counter is specified.
Four types of interval can be selected.