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CHAPTER 1 OVERVIEW
Figure 1.8-2 Timing Chart for Undefined Outputs from Ports 0 and 1 (if the RST Terminal is "H")
Figure 1.8-3 Timing Chart for High Impedance State of Ports 0 and 1 (if the RST Terminal is "L")
r Notes on using the "DIV A, Ri" or "DIVW A, RWi" instruction
The remainder obtained by executing the signed multiplication and division instruction, "DIV A,
Ri" or "DIVW A, RWi" is affected by the bank register and stored at an address of the memory
bank specified in the bank register.
Therefore, the "DIV A, Ri" or "DIVW A, RWi" instruction should be used after setting the
Undefined output period
Vcc (power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Source oscillation signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Falling-edge circuit stabilization wait interval *1
Oscillation stabilization wait interval *2
*1: Falling-edge circuit stabilization wait interval: 217/ Source oscillation frequency
(about 8.19 ms if the source oscillation frequency is 16 MHz)
*2: Oscillation stabilization wait interval: 218/ Source oscillation frequency
(about 16.38 ms if the source oscillation frequency is 16 MHz)
High impedance
Vcc (power supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Source oscillation signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Falling-edge circuit stabilization wait interval *1
Oscillation stabilization wait interval *2
*1: Falling-edge circuit stabilization wait interval: 217/ Source oscillation frequency
(about 8.19 ms if the source oscillation frequency is 16 MHz)
*2: Oscillation stabilization wait interval: 218/ Source oscillation frequency
(about 16.38 ms if the source oscillation frequency is 16 MHz)