
5
1.2 Product Lineup
1.2
Product Lineup
Table 1.2-1 "Product Lineup of the MB90560/565 Series" shows the product lineup of
the MB90560 series. Table 1.2-2 "Product Lineup of the MB90565 Series" shows the product lineup of the MB90565 series.
s Product Lineup
Table 1.2-1 Product Lineup of the MB90560/565 Series
Model
MB90V560
MB90F562/B
MB90562/A
MB90561/A
Type
Evaluation device
Flash Type ROM
Mask ROM Type
ROM size
Not installed
64K bytes
32K bytes
Power supply for
emulators only
(*1)
--
-
RAM size
4K bytes
2K bytes
1K bytes
CPU function
Number of basic instructions: 351
Minimum instruction execution time: 62.5 ns/4 MHz (when PLL clock is multiplied by 4)
Number of addressing modes: 23
Program patch function: 2-address pointer
Maximum memory address space: 16M bytes
Port
I/O ports (CMOS): 51
UART
With a full duplex double buffer.
Capable of synchronous or asynchronous clock transfer.
Also can be used for serial I/O.
Dedicated built-in baud rate generator. Two built-in channels.
16-bit reload
timer
16-bit reload timer operation. Two built-in channels.
Advanced timer
16-bit free running timer x 1 channel
Output compare x 6 channels
Input capture x 4 channels
8/16-bit PPG timer (8-bit mode x 6 channels, 16-bit mode x 3 channels)
Waveform generation circuit: 8-bit timer x 3 channels
Three-phase waveform output with dead time period provided.
8/10-bit A/D
converter
8 channels (input multiplex)
Capable of 8-bit or 10-bit resolution
Conversion time:6.13
s or less (operation at internal 16 MHz clock)
DTP/External
interrupt
8 channels (8 channels can be used for this and A/D input.)
Interrupt cause: L-to-H edge, H-to-L edge, L-level, or H-level selectable
Low-power
consumption
mode
Sleep mode, time-base timer mode, stop mode, and CPU intermittent mode