
415
16.4 8/10-Bit A/D Converter Registers
16.4.1 A/D Control Status Register 1 (ADCS1)
The A/D control status register (ADCS1) sets the A/D conversion activation trigger and
enable/disable of interrupt requests and checks the interrupt request status and
whether the A/D conversion has halted/is in progress.
s Upper Bits of the A/D Control Status Register 1 (ADCS1)
Figure 16.4-2 A/D Control Status Register 1 (ADCS1)
PAUS STS1
STRT RESV
STS0
INTE
0
1
Interrupt request enable bit
Disables interrupt request output.
A/D conversion is halted.
BUSY INT
INTE
INT
Interrupt request flag bit
A/D conversion has not been completed.
A/D conversion has been completed.
Clears interrupt request
No effect on operation
0
1
Reading
Writing
BUSY
Busy bit
A/D conversion is halted.
A/D conversion is in progress.
Stops the A/D conversion.
No change,no effect on other bits.
0
1
Reading
Writing
STRT
A/D conversion activation bit
(valid only when activated by software (ADC2: EXT= 0))
Reserved bit
RESV
Always write 0 to this bit.
R/W R/W R/W R/W R/W R/W
R/W
W
STS1 STS0
A/D activation select bit
0
Activation by software.
Activation by Zero detection of
16-bit free-running timer or activation of software
Activation by 16-bit reload timer1 or
activation of software
Activation by Zero detection of 16-bit
free-running timer, 16-bit reload timer1,
or activation of software
Does not activate the A/D conversion.
Activate the A/D conversion function.
0
1
PAUS
Halt flag bit
(valid only when EI2OS is used)
A/D conversion is active
A/D conversion is halted.
0
1
Address
Initial value
000035 H
00000000 B
R/W : Read/write
W
: Write only
: Initial value
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
1
0
1
0
1