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8.6 Port 3
8.6.2
Operation of Port 3
This section describes the operation of port 3.
s Operation of Port 3
r Setting Port 3 as an output port in the Port 3 direction register (DDR3)
The value stored in the Port 3 data register (PDR3) is output to the Port 3 pin.
If the PDR3 register is read, the value stored in PDR3 register is output.
r Setting Port 3 as an input port in the Port 3 direction register (DDR3)
The Port 3 pin has high impedance.
If the Port 3 data register (PDR3) is set to a value, the value stored in the PDR3 register is
retained but not output to the pin.
If the PDR3 register is read, the pin input level ("0" for "L" or "1" for "H") is output.
Note:
If a read-modify-write instruction (such as the bit set instruction) is used to access the PDR3
register, no bit specified for output in the DDR3 register is affected. For a bit specified for
input in the DDR3 register, however, the pin input level is written to the PDR3 register.
Therefore, to change a bit specified for input to output, first write an output value to the
PDR3 register and then specify the DDR3 register as an output port.
r Port operation after a reset
When the CPU is reset, the DDR3 register is initialized to "00H" and the Port 3 pin has high
impedance.
The PDR3 register is not initialized when the CPU is reset. To use the PDR3 as an output
port, first write an output value to the PDR3 register and then specify the DDR3 register as
an output port.
r Port operation in stop or time-base timer mode
If the port switches to stop mode or timebase timer mode while the pin status setting bit (SPL) of
the low power consumption mode control register (LPMCR) is set to "1", the pins come to have
high impedance regardless of the value in the Port 3 direction register (DDR3). Note that the
input buffer is forcibly shut off to prevent leakage due to an open circuit.