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CHAPTER 15 DELAYED INTERRUPT GEMERATOR MODULE
15.3 Operation of the Delayed Interrupt Generator Module
When the delayed interrupt request output bit (R0) of the delayed interrupt cause/
cancel register (DIRR) is set to "1" using software, a delayed interrupt request is
output to the interrupt controller.
s Operation of the Delayed Interrupt Generator Module
When the delayed interrupt request output bit (R0) of the delayed interrupt cause/cancel register
(DIRR) is set to "1" using software, an interrupt request is output to the interrupt controller. If
interrupt requests other than the delayed interrupt have lower priorities or there is no interrupt
request other than the delayed interrupt request, the interrupt controller outputs an interrupt
request to the CPU. The CPU compares the interrupt request level with the interrupt level mask
register (ILM) in the processor status register (PS). If the interrupt request level is higher than
the interrupt level mask register (ILM), the hardware imbedded processing microprogram is
activated after the instruction currently being executed is completed, to execute the delayed
interrupt processing routine.
If the delayed interrupt request output bit (R0) of the delayed
interrupt cause/cancel register (DIRR) is set to "0" in the interrupt processing routine, the
delayed interrupt cause is cleared and the task is switched.
Figure 15.3-1 Operation of the Delayed Interrupt Generator Module
Delayed interrupt generator module
Interrupt controller
MB90560/566 series CPU
Other requests
ICRyy
IL
CMP
DIRR
ICRxx
ILM
NTA
WRITE
DIRR : Delayed interrupt cause/cancel register
IL
: Interrupt level setting bit in the interrupt control register (ICR)
ILM
: Interrupt level mask register in PS
CMP
: Comparator
ICR
: Interrupt control register