參數(shù)資料
型號(hào): ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 95/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
95 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
9.5.3.3
OTG Interrupt Enable Fall register (S/C: 0380h/0382h)
Table 86
shows the bit allocation of this register that enables interrupts on transition from
HIGH-to-LOW.
[1]
The reserved bits should always be written with the reset value.
9.5.3.4
OTG Interrupt Enable Rise register (S/C: 0384h/0386h)
This register (see
Table 88
for bit allocation) enables interrupts on transition from
LOW-to-HIGH.
Table 86:
Bit
Symbol
OTG Interrupt Enable Fall register: bit allocation
15
14
13
12
11
10
9
8
reserved
[1]
OTG_
SUSPEND
0
R
2
reserved
reserved
B_SE0_
SRP
0
R/S/C
0
VBUS_VLD
Reset
Access
Bit
Symbol
0
0
0
0
0
0
R/S/C
7
B_SESS_
END
0
R/S/C
R/S/C
6
R/S/C
5
R/S/C
4
RMT_
CONN
0
R/S/C
R/S/C
3
ID
R/S/C
1
A_B_SESS
_VLD
0
R/S/C
reserved
Reset
Access
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 87:
Bit
15 to 11
10
9
8
OTG Interrupt Enable Fall register: bit description
Symbol
Description
-
reserved for future use
OTG_SUSPEND
IRQ asserted when the bus exits from the idle state
-
reserved
B_SE0_SRP
IRQ asserted when the bus exits from at least 2 ms of the SE0
state
B_SESS_END
IRQ asserted when V
BUS
> 0.8 V
-
reserved
RMT_CONN
IRQ asserted on RMT_CONN removal
ID
IRQ asserted on the ID pin transition from HIGH to LOW
-
reserved
A_B_SESS_VLD
IRQ asserted on removing A-session valid for the A-device or
B-session valid for the B-device condition
VBUS_VLD
IRQ asserted on the falling edge of V
BUS
7
6 to 5
4
3
2
1
0
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