參數(shù)資料
型號(hào): ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 61/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
61 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 64:
Bit
DW7
63 to 32
DW6
31 to 0
DW5
63 to 32
DW4
31 to 6
5
High-speed bulk IN and OUT, QHA: bit description
Symbol
Access
Description
reserved
-
-
reserved
-
-
reserved
-
-
reserved
J
-
SW —
writes
0; not applicable for QHA.
Jump
:
0 —
To increment the PTD pointer
1 —
To enable the next PTD branching.
Next PTD Counter
: Next PTD branching assigned by the PTD pointer.
4 to 0
NextPTDPointer
[4:0]
SW —
writes
DW3
63
A
SW —
sets
HW —
resets
HW —
writes
HW —
writes
Active
: Write the same value as that in V.
62
61
H
B
Halt
: This bit correspond to the Halt bit of the Status field of QH.
Babble
: This bit correspond to the Babble Detected bit in the Status
field of the iTD, SiTD or QH.
1 —
When babbling is detected, A and V are set to 0.
Error
: This bit corresponds to the Transaction Error bit in the Status
field of iTD, SiTD or QH (Exec_Trans, the signal name is xacterr).
0 —
No PID error.
1 —
If there are PID errors, this bit is set active. The A and V bits are
also set to inactive. This transaction is retried three times.
-
Ping
: For high-speed transactions, this bit corresponds to the Ping
state bit in the Status field of a QH.
0 —
Ping is not set.
1 —
Ping is set.
Software sets this bit to 0.
Data Toggle
: This bit is filled by software to start a PTD. If
NrBytesToTransfer[14:0] is not complete, software needs to read this
value and then write back the same value to continue.
Error Counter
. This field corresponds to the Cerr[1:0] field in QH. The
default value of this field is zero for isochronous transactions.
00 —
The transaction will not retry.
11 —
The transaction will retry three times. Hardware will decrement
these values. When the transaction has tried three times, X error will
be updated.
NAK Counter
. This field corresponds to the NakCnt field in QH.
Software writes for the initial PTD launch. The V bit is reset if NakCnt
decrements to zero and RL is a non-zero value. It reloads from RL if
transaction is ACKed.
-
60
X
HW —
writes
59
58
reserved
P
-
HW —
writes
57
DT
HW —
updates
SW —
writes
56 to 55
Cerr[1:0]
HW —
writes
SW —
writes
54 to 51
NakCnt[3:0]
HW —
writes
SW —
writes
50 to 47
reserved
-
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