參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 121/158頁
文件大小: 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
121 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.7 General registers
10.7.1
DcInterrupt register (R/W: 0218h)
The DcInterrupt register consists of 4 B. The bit allocation is given in
Table 137
.
When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the DcInterrupt register content is nonzero, the INT output
will be asserted. On detecting the interrupt, the external microprocessor must read the
DcInterrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can be individually cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.
Table 136: DMA Burst Counter register: bit description
Bit
Symbol
Description
15 to 13
-
reserved
12 to 0
BURST
COUNTER
[12:0]
32-bit mode.
The value of the burst counter should be programmed so that the buffer
counter is a factor of the burst counter. In the 16-bit mode, DREQ will
drop at every DMA read or write cycle when the burst counter equals 2.
In the 32-bit mode, DREQ will drop at every DMA read or write cycle
when the burst counter equals 4.
Burst Counter
: This register defines the burst length. The counter must
be programmed to be a multiple of two in the 16-bit mode and four in the
Table 137: DcInterrupt register: bit allocation
Bit
31
Symbol
Reset
0
Bus reset
0
Access
R/W
Bit
23
Symbol
EP6TX
Reset
0
Bus reset
0
Access
R/W
Bit
15
Symbol
EP2TX
Reset
0
Bus reset
0
Access
R/W
30
29
28
27
26
25
24
reserved
[1]
EP7TX
0
0
R/W
17
EP3TX
0
0
R/W
9
reserved
[1]
0
0
R/W
EP7RX
0
0
R/W
16
EP3RX
0
0
R/W
8
EP0SETUP
0
0
R/W
0
0
0
0
0
0
0
0
0
0
R/W
22
EP6RX
0
0
R/W
14
EP2RX
0
0
R/W
R/W
21
EP5TX
0
0
R/W
13
EP1TX
0
0
R/W
R/W
20
EP5RX
0
0
R/W
12
EP1RX
0
0
R/W
R/W
19
EP4TX
0
0
R/W
11
EP0TX
0
0
R/W
R/W
18
EP4RX
0
0
R/W
10
EP0RX
0
0
R/W
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