參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 122/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
122 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
Reset
Bus reset
Access
7
6
5
4
3
2
1
0
VBUS
0
0
R/W
DMA
0
0
R/W
HS_STAT
0
0
R/W
RESUME
0
0
R/W
SUSP
0
0
R/W
PSOF
0
0
R/W
SOF
0
0
R/W
BRESET
0
unchanged
R/W
Table 138: DcInterrupt register: bit description
Bit
Symbol
31 to 26
-
25
EP7TX
24
EP7RX
23
EP6TX
22
EP6RX
21
EP5TX
20
EP5RX
19
EP4TX
18
EP4RX
17
EP3TX
16
EP3RX
15
EP2TX
14
EP2RX
13
EP1TX
12
EP1RX
11
EP0TX
10
EP0RX
9
-
8
EP0SETUP
7
VBUS
6
DMA
5
HS_STAT
Description
reserved
Logic 1 indicates the endpoint 7 TX buffer as interrupt source.
Logic 1 indicates the endpoint 7 RX buffer as interrupt source.
Logic 1 indicates the endpoint 6 TX buffer as interrupt source.
Logic 1 indicates the endpoint 6 RX buffer as interrupt source.
Logic 1 indicates the endpoint 5 TX buffer as interrupt source.
Logic 1 indicates the endpoint 5 RX buffer as interrupt source.
Logic 1 indicates the endpoint 4 TX buffer as interrupt source.
Logic 1 indicates the endpoint 4 RX buffer as interrupt source.
Logic 1 indicates the endpoint 3 TX buffer as interrupt source.
Logic 1 indicates the endpoint 3 RX buffer as interrupt source.
Logic 1 indicates the endpoint 2 TX buffer as interrupt source.
Logic 1 indicates the endpoint 2 RX buffer as interrupt source.
Logic 1 indicates the endpoint 1 TX buffer as interrupt source.
Logic 1 indicates the endpoint 1 RX buffer as interrupt source.
Logic 1 indicates the endpoint 0 data TX buffer as interrupt source.
Logic 1 indicates the endpoint 0 data RX buffer as interrupt source.
reserved
Logic 1 indicates that a SETUP token was received on endpoint 0.
Logic 1 indicates V
BUS
is turned on.
DMA status
: Logic 1 indicates a change in the DMA Status register.
High Speed Status:
Logic 1 indicates a change from the full-speed to
high-speed mode (HS connection). This bit is not set, when the system
goes into the full-speed suspend.
Resume status:
Logic 1 indicates that a status change from suspend
to resume (active) was detected.
Suspend status:
Logic 1 indicates that a status change from active to
suspend was detected on the bus.
4
RESUME
3
SUSP
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