參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 18/158頁
文件大小: 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
18 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
The RAM is structured in blocks of PTDs and payloads so that while the USB is executing
on an active transfer-based PTD, the processor can simultaneously fill up another block
area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping
or delaying any other USB transaction or corrupting the RAM data.
Some of the design features are:
The address range of the internal RAM buffer is from 0400h to FFFFh.
The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
All accesses to the internal memory are double-word aligned.
Internal memory address range calculation:
Memory address = (CPU address
0400h) (shift right >> 3). Base address is 0400h.
Table 4:
Memory map
ISO
INT
ATL
Payload
Memory address
CPU address
0400h to 07FFh
0800h to 0BFFh
0C00h to 0FFFh
1000h to FFFFh
Memory address
0000h to 007Fh
0080h to 00FFh
0100h to 017Fh
0180h to 1FFFh
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