參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 54/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
54 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.4.2
HcInterruptEnable register (R/W: 0314h)
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Table 55
.
[1]
The reserved bits should always be written with the reset value.
5
HCSUSP
Host Controller Suspend
: Indicates that the Host Controller has
entered suspend mode.
0 —
No IRQ generated because of the Host Controller entering suspend
mode
1 —
IRQ generated because of the Host Controller entering suspend
mode
If the Interrupt Service Routine (ISR) accesses the ISP1761, it will wake
up for the time specified in bits 31 to 16 of the Power Down Control
register.
reserved; write logic 0
DMA EOT Interrupt
: Indicates DMA transfer completion.
0 —
DMA transfer is not complete
1 —
IRQ asserted because the DMA transfer is complete.
reserved; write logic 0
SOT ITL Interrupt
:
0 —
No SOF event has occurred
1 —
An SOF event has occurred.
4
3
-
DMAEOT
INT
2 to 1
0
-
SOFITLINT
Table 54:
Bit
HcInterrupt register: bit description
…continued
Symbol
Description
Table 55:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
HcInterruptEnable register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
OTG_IRQ_
E
0
R/W
2
ISO_IRQ_
E
0
R/W
1
ATL_IRQ
_E
0
R/W
0
SOFITLINT
_E
0
R/W
Reset
Access
Bit
Symbol
0
0
0
0
0
R/W
7
R/W
6
CLK
R/W
5
R/W
4
R/W
3
INT_IRQ_E
READY _E
0
R/W
HCSUSP_
E
0
R/W
reserved
[1]
DMAEOT
INT _E
0
R/W
reserved
[1]
Reset
Access
0
0
0
0
R/W
R/W
R/W
R/W
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