參數資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數: 139/158頁
文件大小: 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
139 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
15.1.2.3
Multicycle: DMA read
t
a35
t
cy15
DREQ deassertion time after WR_N assertion
last DACK strobe deassertion to next DREQ
assertion time
WR_N pulse width
8.9
82
-
-
ns
ns
t
w15
22
-
ns
Table 171: DMA write (single cycle)
…continued
V
CC(I/O)
= 3.3 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
Min
Max
Unit
DREQ and DACK are active HIGH.
Fig 25. DMA read (multicycle burst)
Table 172: DMA read (multicycle burst)
V
CC(I/O)
= 1.65 V to 1.95 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a16
DACK assertion time after DREQ assertion
t
a26
RD_N assertion time after DACK assertion
t
d16
data valid time after RD_N assertion
t
w16
RD_N pulse width
T
cy16
read-to-read cycle time
t
a36
DREQ deassertion time after last burst RD_N deassertion 20
t
a46
DACK deassertion to next DREQ assertion time
Min
0
0
-
t
d16
40
Max
-
-
31
-
-
-
82
Unit
ns
ns
ns
ns
ns
ns
ns
-
Table 173: DMA read (multicycle burst)
V
CC(I/O)
= 3.3 V to 3.6 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
t
a16
DACK assertion time after DREQ assertion
t
a26
RD_N assertion time after DACK assertion
t
d16
data valid time after RD_N assertion
t
w16
RD_N pulse width
T
cy16
read-to-read cycle time
t
a36
DREQ deassertion time after last burst RD_N deassertion
t
a46
DACK deassertion to next DREQ assertion time
Min
0
0
-
t
d16
36
11
-
Max
-
-
16
-
-
-
82
Unit
ns
ns
ns
ns
ns
ns
ns
DREQ
t
a36
DACK
RD_N
004aaa531
data 0
DATA
data n-1
data 1
data n
t
a16
t
a26
t
d16
t
w16
T
cy16
t
a46
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