參數(shù)資料
型號: ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 19/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
19 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Both the CPU interface logic and the USB Host Controller require access to the internal
ISP1761 RAM at the same time. The internal arbiter controls these accesses to the
internal memory, organized internally on a 64-bit data bus width, allowing a maximum
bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the
CPU interface and the internal USB Host Controller.
7.3 Accessing the ISP1761 Host Controller memory: PIO and DMA
The CPU interface of the ISP1761 can be configured for a 16-bit or 32-bit data bus width.
When the ISP1761 is configured for a 16-bit data bus width, the upper unused 16 data
lines must be pulled up to V
CC(I/O)
. This can be achieved by connecting DATA[31:16] lines
together to a single 10 k
pull-up resistor. The 16-bit or 32-bit data bus width
configuration is done by programming bit 8 of the HW Mode Control register. This will
determine the register and memory access types in both PIO and DMA modes to all
internal blocks: Host Controller, Peripheral Controller and OTG Controller. All accesses
must be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where
one word = 16 bits. When accessing the Host Controller registers in 16-bit mode, the
Fig 6.
Memory segmentation and access block diagram
004aaa568
PTD1
PTD2
PTD32
PTD1
PTD2
.
.
PTD32
PAYLOAD
PAYLOAD
63 kbytes
USB BUS
USB HIGH-SPEED
HOST AND
TRANSACTION
TRANSLATOR
(FULL-SPEED
AND LOW-SPEED)
INTERRUPT
ASYNC
PAYLOAD
PTD32
.
PTD1
PTD2
ISOCHRONOUS
MEMORY MAPPED
INPUT/OUTPUT,
MEMORY
MANAGEMENT
UNIT,
SLAVE DMA
CONTROLLER
AND
INTERRUPT
CONTROL
REGISTERS
ARBITER
control signals
240 MB/s
address
data (64 bits)
D[15:0]/D[31:0]
A[17:1]
.
CS_N
RD_N
WR_N
HC_IRQ
DC_DREQ
DC_IRQ
HC_DREQ
HC_DACK
DC_DACK
MICRO-
PROCESSOR
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