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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
81 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 74:
Bit
DW7
63 to 40
39 to 32
Start and complete split for interrupt: bit description
Symbol
Access
Description
reserved
INT_IN_7[7:0]
-
HW —
writes
-
Bytes received during
μ
SOF7, if
μ
SA[7] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
DW6
31 to 24
INT_IN_6[7:0]
HW —
writes
Bytes received during
μ
SOF6, if
μ
SA[6] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
Bytes received during
μ
SOF5, if
μ
SA[5] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
Bytes received during
μ
SOF4, if
μ
SA[4] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
Bytes received during
μ
SOF3, if
μ
SA[3] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
23 to 16
INT_IN_5[7:0]
HW —
writes
15 to 8
INT_IN_4[7:0]
HW —
writes
7 to 0
INT_IN_3[7:0]
HW —
writes
DW5
63 to 56
INT_IN_2[7:0]
HW —
writes
Bytes received during
μ
SOF2 (bits 7 to 0), if
μ
SA[2] is set to 1 and
frame number is correct. The new value continuously overwrites the old
value.
Bytes received during
μ
SOF1, if
μ
SA[1] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
Bytes received during
μ
SOF0 if
μ
SA[0] is set to 1 and frame number is
correct. The new value continuously overwrites the old value.
All bits can be set to one for every transfer. It specifies which
μ
SOF the
complete split needs to be sent. Valid only for IN. Start split (SS) and
complete split (CS) active bits—
μ
SA = 0000 0001,
μ
S CS = 0000
0100—will cause SS to execute in
μ
Frame0 and CS in
μ
Frame2.
55 to 48
INT_IN_1[7:0]
HW —
writes
47 to 40
INT_IN_0[7:0]
HW —
writes
39 to 32
μ
SCS[7:0]
SW —
writes (0 => 1)
HW —
writes
(1 => 0)
After processing
DW4
31 to 29
28 to 26
25 to 23
22 to 20
19 to 17
16 to 14
13 to 11
10 to 8
Status7[2:0]
Status6[2:0]
Status5[2:0]
Status4[2:0]
Status3[2:0]
Status2[2:0]
Status1[2:0]
Status0[2:0]
HW —
writes
HW —
writes
HW —
writes
HW —
writes
HW —
writes
HW —
writes
HW —
writes
HW —
writes
Interrupt IN or OUT status of
μ
SOF7
Interrupt IN or OUT status of
μ
SOF6
Interrupt IN or OUT status of
μ
SOF5
Interrupt IN or OUT status of
μ
SOF4
Interrupt IN or OUT status of
μ
SOF3
Interrupt IN or OUT status of
μ
SOF2
Interrupt IN or OUT status of
μ
SOF1
Interrupt IN or OUT status of
μ
SOF0
Bit 0 —
Transaction Error (IN and OUT)
Bit 1 —
Babble (IN token only)
Bit 2 —
underrun (OUT token only).
Specifies which
μ
SOF the start split needs to be placed.
For OUT token
: When the frame number of bits DW1(7-3) matches the
frame number of the USB bus, these bits are checked for one before
they are sent for the
μ
SOF.
For IN token
: Only
μ
SOF0,
μ
SOF1,
μ
SOF2 or
μ
SOF3 can be set to 1.
Nothing can be set for
μ
SOF4 and above.
7 to 0
μ
SA[7:0]
SW —
writes (0 => 1)
HW —
writes
(1 => 0)
After processing