參數(shù)資料
型號(hào): ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁數(shù): 12/158頁
文件大?。?/td> 724K
代理商: ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
12 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
A17
105
C12
I
address pin 17
input, 3.3 V tolerant
chip select signal that indicates the area being accessed; active
LOW
input, 3.3 V tolerant
read enable; active LOW
input, 3.3 V tolerant
write enable; active LOW
input, 3.3 V tolerant
digital ground
to indicate the presence of a minimum 3.3 V on pins 6 and 7
(open-drain); connect to V
CC(I/O)
through a 10 k
pull-up resistor
output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant
Peripheral Controller interrupt signal
output 4 mA drive, 3.3 V tolerant
Host Controller interrupt signal
output 4 mA drive, 3.3 V tolerant
DMAC request for the Peripheral Controller
output 4 mA drive, 3.3 V tolerant
DMAC request for Host Controller
output 4 mA drive, 3.3 V tolerant
digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling
capacitor; see
Section 7.7
Host Controller DMA request acknowledgment; when not in use,
connect to V
CC(I/O)
through a 10 k
pull-up resistor
input, 3.3 V tolerant
Peripheral Controller DMA request acknowledgment; when not in
use, connect to V
CC(I/O)
through a 10 k
pull-up resistor
input, 3.3 V tolerant
core power output (1.8 V); internal 1.8 V for the digital core; used for
decoupling; connect a 100 nF capacitor; for details on additional
capacitor placement, see
Section 7.7
Host Controller suspend and wake-up; three-state suspend output
(active LOW) and wake-up input circuits are connected together
HIGH = output is three-state; ISP1761 is in suspend mode
LOW = output is LOW; ISP1761 is not in suspend mode.
connect to V
CC(I/O)
through an external 10 k
pull-up resistor
output pad, open-drain, 4 mA output drive, 3.3 V tolerant
CS_N
106
A12
I
RD_N
107
B12
I
WR_N
108
B11
I
GND
V
BAT_ON_N
109
110
A11
C10
-
OD
DC_IRQ
111
A10
O
HC_IRQ
112
B10
O
DC_DREQ
113
A9
O
HC_DREQ
114
B9
O
V
CC(I/O)
115
C8
P
HC_DACK
116
A8
I
DC_DACK
117
B8
I
V
REG(1V8)
118
B7
P
HC_SUSPEND
/WAKEUP_N
119
A7
I/OD
Table 2:
Symbol
[1]
Pin description
…continued
Pin
LQFP128
Ball
TFBGA128
Type
[2]
Description
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