參數(shù)資料
型號(hào): ISP1761
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus On-The-Go controller
中文描述: 高速通用串行總線和On - The - Go控制器
文件頁(yè)數(shù): 110/158頁(yè)
文件大?。?/td> 724K
代理商: ISP1761
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
110 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Peripheral to host (IN endpoint):
After each write, an internal counter is automatically
incremented by two to the next location in the TX FIFO. When all bytes have been written
(FIFO byte count = endpoint MaxPacketSize), the buffer is automatically validated. The
data packet will then be sent on the next IN token. Whenever required, the Control
Function register (bit VENDP) can validate the endpoint whose byte count is less than
MaxPacketSize.
Host to peripheral (OUT endpoint)
: After each read, an internal counter is automatically
decremented by two to the next location in the RX FIFO. When all bytes have been read,
the buffer contents are automatically cleared. A new data packet can then be received on
the next OUT token. The buffer contents can also be cleared through the Control Function
register (bit CLBUF), whenever it is necessary to forcefully clear the contents.
Remark:
The buffer can be automatically validated or cleared using the Buffer Length
register.
10.5.4
Buffer Length register (R/W: 021Ch)
This register determines the current packet size (DATACOUNT) of the indexed endpoint
FIFO. The bit description is given in
Table 111
.
The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint
MaxPacketSize register is written (see
Table 115
). A smaller value can be written when
required. After a bus reset, the Buffer Length register is made zero.
IN endpoint:
When the data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring data
that is not a multiple of MaxPacketSize. The following two examples demonstrate the
significance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 B and the MaxPacketSize is
programmed as 64 B, the Buffer Length register need not be filled. This is because the
transfer size is a multiple of MaxPacketSize, and the MaxPacketSize packets will be
automatically validated because the last packet is also of MaxPacketSize.
Example 2: Consider that the transfer size is 510 B and the MaxPacketSize is
programmed as 64 B, the Buffer Length register should be filled with 62 B just before the
microcontroller writes the last packet of 62 B. This ensures that the last packet, which is a
short packet of 62 B, is automatically validated.
Use the VENDP bit in the Control register if you are not using the Buffer Length register.
This is applicable only to the PIO mode access.
OUT endpoint:
The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark:
When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
Table 110: Data Port register: bit description
Bit
Symbol
15 to 0 DATAPORT[15:0]
Access
R/W
Value
0000h
Description
Data Port
: A 500 ns delay may be required for
the first read from the Data Port.
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ISP1761BE,518 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE,557 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1761BE518 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP