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| 型號(hào)： | ISP1761 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus On-The-Go controller |
| 中文描述： | 高速通用串行總線和On - The - Go控制器 |
| 文件頁(yè)數(shù)： | 115/158頁(yè) |
| 文件大?。?/td> | 724K |
| 代理商： | ISP1761 |
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9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
115 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6.2
DMA Transfer Counter register (R/W: 0234h)
This 4 B register sets up the total byte count for a DMA transfer (DMACR). It indicates the
remaining number of bytes left for transfer. The bit allocation is given in
Table 123
.
For IN endpoint —
As there is a FIFO in the ISP1761 DMA controller, some data may
remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 B, and the
maximum delay time for the data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint —
Data will not be cleared for the endpoint buffer until all the data has
been read from the DMA FIFO.
Table 120: DMA Command register: bit allocation
Bit
7
Symbol
Reset
1
Bus reset
1
Access
W
6
5
4
DMA_CMD[7:0]
1
1
W
3
2
1
0
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
1
1
W
Table 121: DMA Command register: bit description
Bit
Symbol
7 to 0
DMA_CMD[7:0]
Description
DMA command code; see
Table 122
.
Table 122: DMA commands
Code
Name
00h
GDMA Read
Description
Generic DMA IN token transfer (slave mode only):
Data is
transferred from the external DMA bus to the internal buffer.
Generic DMA OUT token transfer (slave mode only):
Data is
transferred from the internal buffer to the external DMA bus.
reserved
Validate Buffer (for debugging only):
Request from the
microcontroller to validate the endpoint buffer, following a DMA to
USB data transfer.
Clear Buffer:
Request from the microcontroller to clear the
endpoint buffer after a USB to DMA data transfer.
reserved
Reset DMA:
Initializes the DMA core to its power-on reset state.
Remark:
When the DMA core is reset during the Reset DMA
command, the DREQ, DACK, RD_N and WR_N handshake pins
will be temporarily asserted. This can confuse the external DMA
controller. To prevent this, start the external DMA controller
only
after
the DMA reset.
reserved
GDMA stop
: This command stops the GDMA data transfer. Any
data in the OUT endpoint that is not transferred by the DMA will
remain in the buffer. The FIFO data for the IN endpoint will be
written to the endpoint buffer. An interrupt bit will be set to indicate
that the DMA Stop command is complete.
reserved
01h
GDMA Write
02h to 0Dh
0Eh
-
Validate Buffer
0Fh
Clear Buffer
10h
11h
-
Reset DMA
12h
13h
-
GDMA Stop
14h to FFh
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1761BE | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP1761ET | Hi-Speed Universal Serial Bus On-The-Go controller |
| ISP2100A | Telecommunication IC |
| ISP2100BN4 | Microprocessor |
| ISP2300 | Controller Miscellaneous - Datasheet Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1761BE | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,518 | 功能描述:USB 接口集成電路 USB HS OTG CONTROLLER RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,551 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -T OR NO "-" RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE,557 | 功能描述:USB 接口集成電路 USB HS OTG CTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1761BE518 | 制造商:ST-Ericsson 功能描述:IC CONTROLLER USB OTG 128LQFP |
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