參數(shù)資料
型號(hào)： ISP1761
廠商： NXP Semiconductors N.V.
英文描述： Hi-Speed Universal Serial Bus On-The-Go controller
中文描述： 高速通用串行總線和On - The - Go控制器
文件頁數(shù)： 111/158頁
文件大小： 724K
代理商： ISP1761
9397 750 13258
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 12 January 2005
111 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.5.5
DcBufferStatus register (R/W: 021Eh)
This register is accessed using an index. The endpoint index must first be set before
accessing this register for the corresponding endpoint. It reflects the status of the endpoint
FIFO.
Table 112
shows the bit allocation of the DcBufferStatus register.
[1]
The reserved bits should always be written with the reset value.
10.5.6
Endpoint MaxPacketSize register (R/W: 0204h)
This register determines the maximum packet size for all endpoints, except control 0. The
register contains 2 B, and the bit allocation is given in
Table 114
.
Each time the register is written, the Buffer Length registers of all endpoints are
reinitialized to the FFOSZ field value. The NTRANS bits control the number of
transactions allowed in a single microframe (for high-speed isochronous and interrupt
endpoints only).
Table 111: Buffer Length register: bit description
Bit
Symbol
15 to 0 DATACOUNT[15:0]
Access
R/W
Value
0000h
Description
Data Count
: Determines the current packet size
of the indexed endpoint FIFO.
Table 112: DcBufferStatus register: bit allocation
Bit
7
Symbol
Reset
0
Bus reset
0
Access
R/W
6
5
4
3
2
1
0
reserved
[1]
BUF1
0
0
R/W
BUF0
0
0
R/W
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 113: DcBufferStatus register: bit description
Bit
Symbol
Description
7 to 2
-
reserved
1 to 0
BUF[1:0]
Buffer
:
00 —
The buffers are not filled.
01 —
One of the buffers is filled.
10 —
One of the buffers is filled.
11 —
Both the buffers are filled.
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