Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
77
10 Timing Characteristics for 5 V Operation
(continued)
10.2 Reset Circuit
The DSP1627 has a powerup reset circuit that automatically clears the JTAG controller upon powerup. If the supply
voltage falls below V
DD
MIN* and a reset is required, the JTAG controller must be reset—even if the JTAG port isn’t
being used—by applying six low-to-high clock edges on TCK with TMS held high, followed by the usual RSTB and
CKI reset sequence. Figure 12 shows two separate events: an initial powerup and a powerup following a drop in the
power supply voltage.
*
See Table 60, Recommended Operating Condiitons.
Notes:
See Table 62 for CKI electrical requirements and Table 71 for TCK timing requirements.
When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state
condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, DSEL, and RWN outputs remain high, and CKO remains
a free-running clock.
TMS and TDI signals have internal pull-up devices.
Figure 12. Powerup Reset and Chip Reset Timing Diagram
*
T
TCK
= t12 = TCK period. See Table 71 for TCK timing requirements.
With external components as specified in Table 62.
Table 68. Timing Requirements for Powerup Reset and Chip Reset
Abbreviated Reference
t8
t9
t146
Parameter
Min
6T
—
2T
20
20
Max
—
10
—
—
—
—
—
—
—
—
—
95
Unit
ns
ms
ns
ms
μ
s
ns
ns
Reset Pulse (low to high)
V
DD
Ramp
V
DD
MIN to RSTB Low CMOS
Crystal*
Small-signal
t151
t152
TMS High
JTAG Reset to
RSTB Low
6 * T
TCK
2T
CMOS
Crystal*
Small-Signal
20 ms – 6 * T
TCK
if 6 * T
TCK
< 20 ms
0 if 6 * T
TCK
≥
20 ms
20 μs – 6 * T
TCK
if 6 * T
TCK
< 20 μs
0 if 6 * T
TCK
≥
20 μs
—
t153
RSTB Rise (low to high)
ns
5-2253 (F).a
t10
t11
t10
t11
t9
t146
t8
t9
t151
t152
t8
V
DD
RAMP
CKI
TCK
TMS
RSTB
PINSV
OH
V
OL
V
IH
V
IL
V
IH
0.4 V
V
DD
MIN
V
DD
MIN
0.4 V
t153
t153