參數(shù)資料
型號: DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號處理器
文件頁數(shù): 30/154頁
文件大?。?/td> 2365K
代理商: DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
30
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control
register.
Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur.
When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is pow-
ered down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
Figure 7. Power Management Using the powerc and the pllc Registers
CKI2
CRYSTAL
OSCILLATOR,
OR
SMALL SIGNAL
CLOCK
RING
OSCILLATOR
STOP
XTLOFF
MASK-PROGRAMMABLE
OPTION
OFF
CKI
RSTB
CMOS
INPUT
CLOCK
SYNC.
GATE
SLOWCKI
SYNC.
MUX
INTERNAL
PROCESSOR
CLOCK
CLEAR NOCK
DISABLE
INT0
INT0EN
ON
INT1
INT1EN
DEEP
SLEEP
HW STOP
SW STOP
NOCK
PLLEN
PLLSEL
PLL
f
VCO/2
f
SLOW CLOCK
f
INTERNAL CLOCK
f
CKI
DEEP
SLEEP
5-4124 (F).h
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