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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 75/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
75
9 Electrical Characteristics and Requirements
(continued)
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es-
sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh-
old of V
DD
/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec-
ommended that unused input and I/O pins be tied to V
SS
or V
DD
through a 10 k
resistor to avoid application am-
biguities. Further, if I/O pins are tied high or low, they should be pulled fully to V
SS
or V
DD
.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise,
high currents may
flow.
10 Timing Characteristics for 5 V Operation
The following timing characteristics and requirements are preliminary information and are subject to change. Timing
characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions
imposed on the user for proper operation of the device. All timing data is valid for the following conditions:
T
A
= –40
°
C to +85
°
C (See Section 8.3.)
V
DD
= 5 V
±
5%, V
SS
= 0 V (See Section 8.3.)
Capacitance load on outputs (C
L
) = 50 pF, except for CKO, where C
L
= 20 pF.
Output characteristics can be derated as a function of load capacitance (C
L
).
All outputs: 0.03 ns/pF
≤
dt/dC
L
≤
0.06 ns/pF for 10
≤
C
L
≤
100 pF at V
IH
for rising edge and at V
IL
for falling edge.
For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF
x 0.06 ns/pF = 1.2 ns
less
than the specified rise time or delay that includes a rise time.
Test conditions for inputs:
I
Rise and fall times of 4 ns or less
I
Timing reference levels for delays = V
IH
, V
IL
Test conditions for outputs (unless noted otherwise):
I
C
LOAD
= 50 pF; except for CKO, where C
LOAD
= 20 pF
I
Timing reference levels for delays = V
IH
, V
IL
I
3-state delays measured to the high-impedance state of the output driver
For the timing diagrams, see Table 62 for input clock requirements.
Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.
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