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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 150/154頁(yè) |
| 文件大小： | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
150
Lucent Technologies Inc.
13 Crystal Electrical Characteristics and Requirements
(continued)
Note that for a given crystal, the pullability can be reduced, and, hence, the frequency stability improved, by making
CL as large as possible while still maintaining sufficient negative resistance to ensure start-up per the curves shown
in Figures 86 and 87.
Since it is not possible to know the exact values of the parasitic capacitance in a crystal-based oscillator system, the
external capacitors are usually selected empirically to null out the frequency offset on a typical prototype board.
Thus, if a crystal is specified to operate with a load capacitance of 10 pF, the external capacitors would have to be
made slightly less than 20 pF each in order to account for strays. Suppose, for instance, that a crystal for which
C
L
= 10 pF is specified is plugged into the system and it is determined empirical that the best frequency accuracy
occurs with Cext = 18 pF. This would mean that the equivalent board and device strays from each leac to ground
would be 2 pF.
As an example, suppose it is desired to design a 23 MHz, 3.3 V system with
±
100 ppm frequency accuracy. The
parameters for a typical high-accuracy, custom, 23 MHz fundamental mode crystal are as follows:
Initial Tolerance
Temperature Tolerance
Aging Tolerance
Series Resistance
Motional Capacitance (C
1
)
Parasitic Capacitance (C
0
)
10 ppm
25 ppm
6 ppm
20
max.
15 fF max.
7 pF max.
In order to ensure oscillator start-up, the negative resistance of the oscillator with load and parasitic capacitance
must be at least twice the series resistance of the crystal, or 40
. Interpolating from Figure 89, external capacitors
plus strays can be made as large as 30 pF while still achieving 40
of negative resistance. Assume for this example
that external capacitors are chosen so that the total load capacitance including strays is 30 pF per lead, or 15 pF
total. Thus, a load capacitance, C
L
= 15 pF would be specified to the crystal manufacturer.
From the above equation, the pullability would be calculated as follows:
If 2% external capacitors are used, the frequency deviation due to capacitor tolerance is equal to:
(0.02)(15 pF)(15.5 ppm/pF) = 4.7 ppm
Note:
To simplify analysis, C
ext
is considered to be 30 pF. In practice, it would be slightly less than this value to
account for strays. Also, temperature and aging tolerances on the capacitors have been neglected.
Typical capacitance variation of the oscillator circuit in the DSP1627 itself across process, temperature, and supply
voltage is
±
1 pF. Thus, the expected frequency variation due to the DSP1627 is:
(1 pF)(15.5 ppm/pF) = 15.5 ppm
Approximate variation in parasitic capacitance of crystal =
±
0.5 pF.
Frequency shift due to variation in C
0
= (0.5 pF)(15.5 ppm/pF) = 7.75 ppm
Approximate variation in parasitic capacitance of printed-circuit board =
±
1.5 pF.
Frequency shift due to variation in board capacitance = (1.5 pF)(15.5 ppm/pF) = 23.25 ppm
pullability
C
10
6
C
L
+
)
2
2 C
0
--------------------------------
0.015
2 7
-------------------- 10
6
15
)
+
)
2
15.5 ppm/pF
=
=
=
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