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參數(shù)資料
| 型號： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號處理器 |
| 文件頁數(shù)： | 14/154頁 |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
14
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
Interruptibility
Vectored interrupts are serviced only after the execution
of an interruptible instruction. If more than one vectored
interrupt is asserted at the same time, the interrupts are
serviced sequentially according to their assigned priori-
ties. See Table 4 for the priorities assigned to the vec-
tored interrupts. Interrupt service routines, branch and
conditional branch instructions, cache loops, and in-
structions that only decrement one of the RAM pointers,
r0 to r3 (e.g., *r3
), are not interruptible.
A trap is similar to an interrupt, but it gains control of the
processor by branching to the trap service routine even
when the current instruction is noninterruptible. It may
not be possible to return to normal instruction execution
from the trap service routine since the machine state
cannot always be saved. In particular, program execu-
tion cannot be continued from a trapped cache loop or
interrupt service routine. While in a trap service routine,
another trap is ignored.
When set to 1, the status bits in the ins register indicate
that an interrupt has occurred. The processor must
reach an interruptible state (completion of an interrupt-
ible instruction) before an enabled vectored interrupt will
be acted on. An interrupt will not be serviced if it is not
enabled. Polled interrupt service can be implemented
by disabling the interrupt in the inc register and then
polling the ins register for the expected event.
Vectored Interrupts
Tables 29 and 30 show the inc and ins registers. A logic
1 written to any bit of inc enables (or unmasks) the as-
sociated interrupt. If the bit is cleared to a logic 0, the in-
terrupt is masked. Note that neither the software
interrupt nor traps can be masked.
The occurrence of an interrupt that is not masked will
cause the program execution to transfer to the memory
location pointed to by that interrupt's vector address, as-
suming no other interrupt is being serviced (see Table
4, Interrupt Vector Table). The occurrence of an inter-
rupt that is masked causes no automatic processor ac-
tion, but will set the corresponding status bit in the ins
register. If a masked interrupt occurs, it is latched in the
ins register, but the interrupt is not taken. When un-
latched, this latched interrupt will initiate automatic pro-
cessor interrupt action. See the DSP1611/17/18/27
Digital Signal Processor Information Manual or a more
detailed description of the interrupts.
Signaling Interrupt Service Status
Five pins of DSP1627 are devoted to signaling interrupt
service status. The IACK pin goes high while any inter-
rupt or user trap is being serviced, and goes low when
the ireturn instruction from the service routine is issued.
Four pins, VEC[3:0], carry a code indicating which of the
interrupts or trap is being serviced. Table 4 contains the
encodings used by each interrupt.
Traps due to HDS breakpoints have no effect on either
the IACK or VEC[3:0] pins. Instead, they show the inter-
rupt state or interrupt source of the DSP when the trap
occurred.
Clearing Interrupts
The PHIF interrupts (PIBF and POBE) are cleared by
reading or writing the parallel host interface data trans-
mit registers pdx0[in] and pdx0[out], respectively. The
SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE2)
are cleared by reading or writing, as appropriate, the se-
rial data registers sdx[in], sdx2[in], sdx[out], and
sdx2[out]. The JTAG interrupt (JINT) is cleared by read-
ing the jtag register.
Three of the vectored interrupts are cleared by writing to
the ins register. Writing a 1 to the INT0, INT1, or TIME
bits in the ins will cause the corresponding interrupt sta-
tus bit to be cleared to a logic 0. The status bit for these
vectored interrupts is also cleared when the ireturn in-
struction is executed, leaving set any other vectored in-
terrupts that are pending.
Traps
The TRAP pin of the DSP1627 is a bidirectional signal.
At reset, it is configured as an input to the processor.
Asserting the TRAP pin will force a user trap. The trap
mechanism is used for two purposes. It can be used by
an application to rapidly gain control of the processor for
asynchronous time-critical event handling (typically for
catastrophic error recovery). It is also used by the HDS
for breakpointing and gaining control of the processor.
Separate vectors are provided for the user trap (0x46)
and the HDS trap (0x3). Traps are not maskable.
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