參數(shù)資料
型號： DSP1627
英文描述： TVS 400W 6.5V BIDIRECT SMA
中文描述： DSP1627數(shù)字信號處理器
文件頁數(shù)： 42/154頁
文件大?。?/td> 2365K
代理商： DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
42
Lucent Technologies Inc.
5 Software Architecture
(continued)
I
Barrel Shifter:
aD = aS >> IM16
aD = aS >> arM
aD = aS >> aS
Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word.
Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.
Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.
aD = aS >>> IM16
aD = aS >>> arM
aD = aS >>> aS
Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word.
Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle.
Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.
aD = aS << IM16
aD = aS << arM
aD = aS << aS
Arithmetic left shift
by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
Arithmetic left shift
by arM (36-bit shift, 0s filled in); 1-cycle.
Arithmetic left shift
by aS (36-bit shift, 0s filled in); 2-cycle.
aD = aS <<< IM16
aD = aS <<< arM
aD = aS <<< aS
Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.
Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle.
Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle.
Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended.
I
Normalization and Exponent Computation:
aD = exp(aS)
aD = norm(aS, arM)
Detect the number of redundant sign bits in accumulator; 1-cycle.
Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.
I
Bit Field Extraction and Insertion:
aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word.
aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle.
aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word.
aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle.
aD = insert(aS, IM16)
aD = insert(aS, arM)
Bit field insertion, field specified as immediate; 2-cycle, 2-word.
Bit field insertion, field specified in arM; 2-cycle.
Note:
The bit field to be inserted or extracted is specified as follows. The width (in bits) of the field is the upper byte
of the operand (immediate or arM), and the offset from the LSB is in the lower byte.
I
Alternate Accumulator Set:
aD = aS:aa0
aD = aS:aa1
Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle.
Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle.
Note:
The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator.
Table 19. Replacement Table for F3 ALU Instructions and F4 BMU Instructions
Replace
aD, aT, aS
IM16
arM
Value
a0 or a1
immediate
ar<0—3>
Meaning
One of the two accumulators.
16-bit data, sign-, zero-, or one-extended as appropriate.
One of the auxiliary BMU registers.
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