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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 31/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
31
4 Hardware Architecture
(continued)
Await Bit of the alf Register
Setting the AWAIT bit of the alf register causes the pro-
cessor to go into the standard sleep state or power-sav-
ing standby mode. Operation of the AWAIT bit is the
same as in the DSP1610, DSP1611, DSP1616,
DSP1617, and DSP1618. In this mode, the minimum
circuitry required to process an incoming interrupt re-
mains active, and the PLL remains active if enabled. An
interrupt will return the processor to the previous state,
and program execution will continue. The action result-
ing from setting the AWAIT bit and the action resulting
from setting bits in the powerc register are mostly inde-
pendent. As long as the processor is receiving a clock,
whether slow or fast, the DSP may be put into standard
sleep mode with the AWAIT bit. Once the AWAIT bit is
set, the STOP pin can be used to stop and later restart
the processor clock, returning to the standard sleep
state. If the processor clock is not running, however, the
AWAIT bit cannot be set.
Power Management Sequencing
There are important considerations for sequencing the
power management modes. Both the crystal oscillator
and the small-signal clock input circuits have start-up
delays which must be taken into account, and the PLL
requires a delay to reach lock-in. Also, the chip may or
may not need to be reset following a return from a low-
power state.
Devices with a crystal oscillator or small-signal input
clocking option may use the XTLOFF bit in the powerc
register to power down the on-chip oscillator or small-
signal circuitry, thereby reducing the power dissipation.
When reenabling the oscillator or the small-signal cir-
cuitry, it is important to bear in mind that a start-up inter-
val exists during which time the clocks are not stable.
Two scenarios exist here:
1. Immediate Turn-Off, Turn-On with RSTB: This sce-
nario applies to situations where the target device is
not required to execute any code while the crystal os-
cillator or small-signal input circuit is powered down
and where restart from a reset state can be tolerated.
In this case, the processor clock derived from either
the oscillator or the small-signal input is running when
XTLOFF is asserted. This effectively stops the inter-
nal processor clock. When the system chooses to re-
enable the oscillator or small-signal input, a reset of
the device will be required. The reset pulse must be
of sufficient duration for the oscillator start-up interval
to be satisfied. A similar interval is required for the
small-signal input circuit to reach its dc operating
point. A minimum reset pulse of 20 ms will be ade-
quate. The falling edge of the reset signal, RSTB, will
asynchronously clear the XTLOFF field, thus re-en-
abling the power to the oscillator or small-signal cir-
cuitry. The target DSP will then start execution from a
reset state, following the rising edge of RSTB.
2. Running from Slow Clock While XTLOFF Active: The
second scenario applies to situations where the de-
vice needs to continue execution of its target code
when the crystal oscillator or small-signal input is
powered down. In this case, the device switches to
the slow ring oscillator clock first, by enabling the
SLOWCKI field before writing a 1 to the XTLOFF
field. Two
nop
s are needed in between the two write
operations to the powerc register. The target device
will then continue execution of its code at slow speed,
while the crystal oscillator or small-signal input clock
is turned off. Switching from the slow clock back to
the high-speed crystal oscillator clock is then accom-
plished in three user steps. First, XTLOFF is cleared.
Then, a user-programmed routine sets the internal
timer to a delay to wait for the crystal's oscillations to
become stable. When the timer counts down to zero,
the high-speed clock is selected by clearing the
SLOWCKI field, either in the timer's interrupt service
routine or following a timer polling loop. If PLL opera-
tion is desired, then an additional routine is neces-
sary to enable the PLL and wait for it to lock.
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