參數(shù)資料
型號: DSP1627
英文描述: TVS 400W 6.5V BIDIRECT SMA
中文描述: DSP1627數(shù)字信號處理器
文件頁數(shù): 50/154頁
文件大?。?/td> 2365K
代理商: DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
50
Lucent Technologies Inc.
5 Software Architecture
(continued)
Table 31. timerc Register
Bit
Field
15—7
RSVD
6
5
4
3—0
DISABLE
RELOAD
T0EN
PRESCALE
Field
DISABLE
Value
0
1
0
1
0
1
Description
Timer enabled.
Timer and prescaler disabled. The period register and timer0 are not reset.
Timer stops after counting down to 0.
Timer automatically reloads and repeats indefinitely.
Timer holds current count.
Timer counts down to 0.
See table below.
RELOAD
T0EN
PRESCALE
PRESCALE Field
PRESCALE
Frequency of
Timer Interrupts
CKO/2
CKO/4
CKO/8
CKO/16
CKO/32
CKO/64
CKO/128
CKO/256
PRESCALE
Frequency of
Timer Interrupts
CKO/512
CKO/1024
CKO/2048
CKO/4096
CKO/8192
CKO/16384
CKO/32768
CKO/65536
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 32. Phase-Locked Loop Control (pllc) Register
Bit
Field
15
14
13
ICP
12
11—8
LF[3:0]
7—5
4—0
PLLEN
PLLSEL
SEL5V
Nbits[2:0]
Mbits[4:0]
Field
PLLEN
Value
0
1
0
1
0
1
Description
PLL powered down.
PLL powered up.
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
Charge pump current selection (see Table 64 for proper value).
3 V operation (see Table 64 for proper value).
5 V operation (see Table 64 for proper value).
Loop filter setting (see Table 64 for proper value).
Encodes N, 1
N
8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1.
Encodes M, 2
M
20, where M = Mbits[4:0] + 2, f
INTERNAL CLOCK
= f
CKI
x (M/(2N)).
PLLSEL
ICP
SEL5V
LF[3:0]
Nbits[2:0]
Mbits[4:0]
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