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參數(shù)資料
| 型號(hào)： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 19/154頁(yè) |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
19
4 Hardware Architecture
(continued)
programmed in the mwait register. For example, let two
instructions be executed: the first reads a coefficient
from EROM and writes data to ERAM; the second reads
a coefficient from EROM and reads data from ERAM.
The sequencer carries out the following steps at the ex-
ternal memory interface: read EROM, write ERAM, read
EROM, and read ERAM. Each step is done in sequen-
tial one-instruction cycle steps, assuming zero wait-
states are programmed. Note that the number of in-
struction cycles taken by the two instructions is four. Al-
so, in this case, the write hold time is zero.
The DSP1627 allows writing into external instruction/
coefficient memory. By setting bit 11, WEROM, of the
ioc register (see Table 38), writing to (or reading from)
data memory or memory-mapped I/O asserts the
EROM strobe instead of ERAMLO, IO, or ERAMHI.
Therefore, with WEROM set, EROM appears in both Y
space (replacing ERAM) and X space, in its normal po-
sition.
Bit 14 of the ioc register (see Table 38), EXTROM, may
be used with WEROM to download to a full 64K of ex-
ternal memory. When WEROM and EXTROM are both
asserted, address bit 15 (AB15) is held low, aliasing the
upper 32K of external memory into the lower 32K.
When an access to internal memory is made, the
AB[15:0] bus holds the last valid external memory ad-
dress. Asserting the RSTB pin low 3-states the AB[15:0]
bus. After reset, the AB[15:0] value is undefined.
The leading edge of the memory segment enables can
be delayed by approximately one-half a CKO period by
programming the ioc register (see Table 38). This is
used to avoid a situation in which two devices drive the
data bus simultaneously.
Bits 7, 8, and 13 of the ioc register select the mode of
operation for the CKO pin (see Table 38). Available op-
tions are a free-running unstretched clock, a wait-stated
sequenced clock (runs through two complete cycles
during a sequenced external memory access), and a
wait-stated clock based on the internal instruction cycle.
These clocks drop to the low-speed internal ring oscilla-
tor when SLOWCKI is enabled (see 4.13, Power Man-
agement). The high-to-low transitions of the wait-stated
clock are synchronized to the high-to-low transition of
the free-running clock. Also, the CKO pin provides ei-
ther a continuously high level, a continuously low level,
or changes at the rate of the internal processor clock.
This last option, only available with the crystal and
small-signal input clock options, enables the DSP1627
CKI input buffer to deliver a full-rate clock to other devic-
es while the DSP1627 itself is in one of the low-power
modes.
4.6 Bit Manipulation Unit (BMU)
The BMU interfaces directly to the main accumulators in
the DAU providing the following features:
I
Barrel shifting—logical and arithmetic, left and right
shift
I
Normalization and extraction of exponent
I
Bit-field extraction and insertion
These features increase the efficiency of the DSP in ap-
plications such as control or data encoding and decod-
ing. For example, data packing and unpacking, in which
short data words are packed into one 16-bit word for
more efficient memory storage, is very easy.
In addition, the BMU provides two auxiliary accumula-
tors, aa0 and aa1. In one instruction cycle, 36-bit data
can be shuffled, or swapped, between one of the main
accumulators and one of the alternate accumulators.
The ar<0—3> registers are 16-bit registers that control
the operations of the BMU. They store a value that de-
termines the amount of shift or the width and offset
fields for bit extraction or insertion. Certain operations in
the BMU set flags in the DAU psw register and the alf
register (see Table 26, Processor Status Word (psw)
Register, and Table 35, alf Register). The ar<0—3> reg-
isters can also be used as general-purpose registers.
The BMU instructions are detailed in Section 5.1. For a
thorough description of the BMU, see the DSP1611/17/
18/27 Digital Signal Processor Information Manual.
4.7 Serial I/O Units (SIOs)
The serial I/O ports on the DSP1627 device provide a
serial interface to many codecs and signal processors
with little, if any, external hardware required. Each high-
speed, double-buffered port (sdx and sdx2) supports
back-to-back transmissions of data. SIO and SIO2 are
identical. The output buffer empty (OBE and OBE2) and
input buffer full (IBF and IBF2) flags facilitate the read-
ing and/or writing of each serial I/O port by program-
or interrupt-driven I/O. There are four selectable active
clock speeds.
A bit-reversal mode provides compatibility with either
the most significant bit (MSB) first or least significant bit
(LSB) first serial I/O formats (see Table 22, Serial I/O
Control Registers (sioc and sioc2)). A multiprocessor
I/O configuration is supported. This feature allows up to
eight DSP161X devices to be connected together on an
SIO port without requiring external glue logic.
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