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參數(shù)資料
| 型號： | DSP1627 |
| 英文描述： | TVS 400W 6.5V BIDIRECT SMA |
| 中文描述： | DSP1627數(shù)字信號處理器 |
| 文件頁數(shù)： | 21/154頁 |
| 文件大?。?/td> | 2365K |
| 代理商： | DSP1627 |
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Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
21
4 Hardware Architecture
(continued)
In order to prevent multiple bus drivers, only one DSP
can be programmed to transmit in a particular time slot.
In addition, it is important to note that the address/pro-
tocol channel is 3-stated in any time slot that is not being
driven.
Therefore, to prevent spurious inputs, the address/pro-
tocol channel should be pulled up to V
DD
with a 5 k
re-
sistor, or it should be guaranteed that the bus is driven
in every time slot. (If the SYNC1 signal is externally gen-
erated, then this pull-up is required for correct initializa-
tion.)
Each SIO also has a fully decoded transmitting address
specified by the srta register transmit address field (bits
7—0). This is used to transmit information regarding the
destination(s) of the data. The fully decoded receive ad-
dress specified by the srta register receive address field
(bits 15—8) determines which data will be received.
The SIO protocol channel data is controlled via the sad-
dx register. When the saddx register is written, the
lower 8 bits contain the 8-bit protocol field. On a read,
the high-order 8 bits read from saddx are the most re-
cently received protocol field sent from the transmitting
DSP's saddx output register. The low-order 8 bits are
read as 0s.
An example use of the protocol channel is to use the top
3 bits of the saddx value as an encoded source address
for the DSPs on the multiprocessor bus. This leaves the
remaining 5 bits available to convey additional control
information, such as whether the associated field is an
opcode or data, or whether it is the last word in a trans-
fer, etc. These bits can also be used to transfer parity in-
formation about the data. Alternatively, the entire field
can be used for data transmission, boosting the band-
width of the port by 50%.
Using SIO2
The SIO2 functions the same as the SIO. Please refer
to Pin Multiplexing in Section 4.1 for a description of pin
multiplexing of BIO, PHIF, VEC[3:0], and SIO2.
Figure 5. Multiprocessor Communication and Connections
DSP 0
D
I
S
S
DSP 1
DSP 7
DATA CHANNEL
CLOCK
ADDRESS/PROTOCOL CHANNEL
SYNC SIGNAL
D
O
D
I
S
S
D
O
D
I
S
S
D
O
5 k
V
DD
5-4181 (F).a
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