參數(shù)資料
型號： DSP1627
英文描述： TVS 400W 6.5V BIDIRECT SMA
中文描述： DSP1627數(shù)字信號處理器
文件頁數(shù)： 35/154頁
文件大?。?/td> 2365K
代理商： DSP1627
Data Sheet
March 2000
DSP1627 Digital Signal Processor
Lucent Technologies Inc.
35
4 Hardware Architecture
(continued)
Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled, PLL Disabled
. If the target de-
vice contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to
further reduce power. In this case, the slow clock must be selected first, and then the PLL must be disabled, since
the PLL cannot run without the clock input circuitry being active.
powerc = 0x40F0
2*nop
pllc = 0x29F2
powerc = 0xC0F0
sleep:a0 = 0x8000
do 1 {
alf = a0
nop
}
nop
nop
powerc = 0x40F0
call xtlwait
pllc = 0xE9F2
call pllwait
cont: powerc = 0x00F0
2*nop
powerc = 0x0000
/* Turn off peripherals and select slow clock */
/* Wait for slow clock to take effect */
/* Disable PLL (assume N = 1,M = 20, LF = 1001) */
/* Disable crystal oscillator */
/* Set alf register in cache loop if running from */
/* external memory with >1 wait state */
/* Stop internal processor clock, interrupt circuits */
/* active */
/* Needed for bedtime execution. Reduced sleep power
/* consumed here.... Interrupt wakes up device */
/* Clear XTLOFF, leave PLL disabled */
/* Wait until crystal oscillator/small-signal is stable */
/* Enable PLL, continue to run off slow clock */
/* Loop to check for LOCK flag assertion */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Turn peripherals back on */
Software Stop, PLL Disabled
. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to
reenable the clocks. If the device uses the crystal oscillator or small-signal clock option, the power management
must be done in the correct sequence, with the PLL being disabled before shutting down the clock input buffer.
powerc = 0x4000
2*nop
pllc = 0x29F2
powerc = 0xD000
/* SLOWCKI asserted */
/* Wait for slow clock to take effect */
/* Disable PLL (assume N = 1, M = 20, LF = 1001) */
/* XTLOFF asserted, if applicable and INT0EN
/* asserted */
/* NOCK asserted, all clocks stop */
/* Minimum switching power consumed here */
/* Some nops will be needed */
/* INT0 pin clears NOCK field, clocking resumes */
/* INTOEN cleared and XTLOFF cleared, if applicable */
/* Wait until crystal oscillator/small-signal is stable */
/* if applicable */
/* Enable PLL, continue to run off slow clock */
/* Loop to check for LOCK flag assertion */
/* Select high-speed PLL based clock */
/* Wait for it to take effect */
/* Clear the INT0 status bit */
sopor:powerc = 0xF000
3*nop
cont: powerc = 0x4000
call xtlwait
pllc = 0xE9F2
call pllwait
powerc = 0x0
2*nop
ins = 0x0010
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