參數(shù)資料
型號: 82559
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196
封裝: 15 X 15 MM, BGA-196
文件頁數(shù): 83/124頁
文件大?。?/td> 1332K
代理商: 82559
Networking Silicon — 82559
Datasheet
73
9.1.1
System Control Block Status Word
The System Control Block (SCB) Status Word contains status information relating to the 82559’s
Command and Receive units.
9.1.2
System Control Block Command Word
Commands for the 82559’s Command and Receive units are placed in this register by the CPU.
Bits
Name
Description
15
CX
Command Unit (CU) Executed.
The CX bit indicates that the CU has
completed executing a command with its interrupt bit set.
14
FR
Frame Received.
The FR bit indicates that the Receive Unit (RU) has
finished receiving a frame.
13
CNA
CU Not Active.
The CNA bit is set when the CU is no longer active and in
either an idle or suspended state.
12
RNR
Receive Not Ready.
The RNR bit is set when the RU is not in the ready
state. This may be caused by an RU Abort command, a no resources
situation, or set suspend bit due to a filled Receive Frame Descriptor.
11
MDI
Management Data Interrupt.
The MDI bit is set when a Management Data
Interface read or write cycle has completed. The management data interrupt
is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
10
SWI
Software Interrupt.
The SWI bit is set when software generates an
interrupt.
9
ER
Early Receive.
The ER bit is used for early receive interrupts.
8
FCP
Flow Control Pause.
The FCP bit is used as the flow control pause bit.
7:6
CUS
Command Unit Status.
The CUS field contains the status of the Command
Unit.
5:2
RUS
Receive Unit Status.
The RUS field contains the status of the Receive Unit.
1:0
Reserved
These bits are reserved and should be set to 00b.
Bits
Name
Description
31:26
Specific
Interrupt Mask
Specific Interrupt Mask.
Setting this bit to 1b causes the 82559 to stop
generating an interrupt (in other words, de-assert the INTA# signal) on the
corresponding event.
25
SI
Software Generated Interrupt.
Setting this bit to 1b causes the 82559 to
generate an interrupt. Writing a 0b to this bit has no effect.
24
M
Interrupt Mask.
If the Interrupt Mask bit is set to 1b, the 82559 will not
assert its INTA# pin. The M bit has higher precedence that the Specific
Interrupt Mask bits and the SI bit.
23:20
CUC
Command Unit Command.
This field contains the CU command.
19
Reserved
This bit is reserved and should be set to 0b.
18:16
RUC
Receive Unit Command.
This field contains the RU command.
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