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參數(shù)資料
| 型號： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 74/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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82559 — Networking Silicon
64
Datasheet
8.1.21
Power Management Control/Status Register (PMCSR)
The Power Management Control/Status is a word register. It is used to determine and change the
current power state of the 82559 and control the power management interrupts in a standard
manner.
8.1.22
Data Register
The data register is an 8-bit read only register that provides a mechanism for the 82559 to report
state dependent maximum power consumption and heat dissipation. The value reported in this
register depends on the value written to the Data Select field in the PMCSR register. The power
measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution
according to the Data Scale. The value in this register is hard coded in the silicon. The structure of
the data register differs between the 82559 B-step and C-step. The are presented below in
Table 10
and
Table 11
, respectively.
Table 9. Power Management Control and Status Register
Bits
Default
Read/Write
Description
15
0b
Read/Clear
PME Status.
This bit is set upon a wake-up event. It is independent of
the state of the PME Enable bit. If 1b is written to this bit, the bit will be
cleared. It also de-asserts the PME# signal and clears the PME status
bit in the Power Management Driver Register. When the PME# signal
is enabled, the PME# signal reflects the state of the PME status bit.
In a CardBus system, writing a 1b to this bit clears the GWAKE bit in
the Function Event register. The Function Event register is described in
Section 9.1.14.1, “LAN Function Event Register” on page 77
.
14:13
00b
Read Only
Data Scale.
This field indicates the data register scaling factor. It
equals 10b for registers zero through eight and 00b for registers nine
through fifteen.
12:9
0000b
Read Only
Data Select.
This field is used to select which data is reported through
the Data register and Data Scale field.
8
0b
Read Clear
PME Enable.
This bit enables the 82559 to assert PME#.
7:5
000b
Read Only
Reserved
. These bits are reserved and should be set to 000b.
4
0b
Read Only
Dynamic Data.
The 82559 does not support the ability to monitor the
power consumption dynamically.
3:2
00b
Read Only
Reserved.
These bits are reserved and should be set to 00b.
1:0
00b
Read/Write
Power State.
This 2-bit field is used to determine the current power
state of the 82559 and to set the 82559 into a new power state. The
definition of the field values is as follows.
00 - D0
01 - D1
10 - D2
11 - D3
Table 10. 82559 B-step Ethernet Data Register
Data Select
Data Scale
Data Reported
0
2
D0 Power Consumption = 58 (580 mW)
1
2
D1 Power Consumption = 40 (400 mW)
2
2
D2 Power Consumption = 40 (400 mW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8255A-5 | PROGRAMMABLE PERIPHEAL INTERFACE |
| 8255A | IC LOGIC 3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER -40+85C SSOP-16 - OBSOLETE |
| 8255A | Programmable Peripheral Interface iAPX86 Family |
| 8255A-5 | 12-Bit, 2.7 V to 5.25 V, 1.5 MSPS Low Power ADC; Package: SOIC - Wide; No of Pins: 24; Temperature Range: Industrial |
| 82562G | Mbps Platform LAN Connect |
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