參數(shù)資料
型號： 82559
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196
封裝： 15 X 15 MM, BGA-196
文件頁數(shù)： 31/124頁
文件大?。?/td> 1332K
代理商： 82559
Networking Silicon — 82559
Datasheet
21
Note:
The 82559 is considered the target in the above diagram; thus, TRDY# is not asserted.
A Retry may also occur in the following two scenarios:
Card Information Structure (CIS) in memory is accessed in CardBus mode.
External modem registers are accessed and the modem does not assert IOCHRDY within 7
PCI clocks from the assertion of MDMCS#.
4.2.1.1.4
Error Handling
Data Parity Errors:
The 82559 checks for data parity errors while it is the target of the
transaction. If an error was detected, the 82559 always sets the Detected Parity Error bit in the PCI
Configuration Status register, bit 15. The 82559 also asserts PERR#, if the Parity Error Response
bit is set (PCI Configuration Command register, bit 6). The 82559 does not attempt to terminate a
cycle in which a parity error was detected. This gives the initiator the option of recovery.
Target-Disconnect:
The 82559 prematurely terminate a cycle in the following cases:
After accesses to the Flash buffer
After accesses to its CSR
After accesses to the configuration space
System Error:
The 82559 reports parity error during the address phase using the SERR# pin. If the
SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit are
not set, the 82559 only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
If SERR# Enable and Parity Error Response bits are both set, the 82559 sets the Signaled System
Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and
asserts SERR# for one clock.
The 82559, when detecting system error, will claim the cycle if it was the target of the transaction
and continue the transaction as if the address was correct.
Note:
The 82559 will report a system error for any parity error during an address phase, whether or not it
is involved in the current transaction.
Figure 6. PCI Retry Cycle
S
8
CLK
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
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