參數(shù)資料
型號: 82559
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器)
中文描述: 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196
封裝: 15 X 15 MM, BGA-196
文件頁數(shù): 39/124頁
文件大?。?/td> 1332K
代理商: 82559
Networking Silicon — 82559
Datasheet
29
In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In
network adapter implementations, the PCI power good signal can be generated locally using an
external analog device. In these designs, the ISOLATE# signal should “envelope” the system’s PCI
power good signal as shown in
Figure 9
.
In many systems, the PCI RST# signal is asserted low whenever the PCI bus is inactive. In these
systems, the 82559 B-step device and later devices allow the ISOLATE# pin to be driven from the
PCI RST# signal. In this case, the ALTRST# pin on the 82559 should be pulled high to the PCI bus
high voltage level.
4.3.1.4.4
PCI Reset Signal
The PCI RST# signal may be activated in one of the following cases:
Power-up
Warm boot
Wake-up (B3 to B0 transition)
Set to power-down (B0 to B3 transition)
If PME is enabled (in the PCI power management registers), the RST# signal does not affect any
PME related circuits (in other words, the CSTSCHG registers (CardBus only), PCI power
management registers, and the wake-up packet would not be affected). While the RST# signal is
active, the 82559 ignores other PCI signals and floats its outputs. However, if AUXPWR is
asserted, the RST# signal has no affect on any circuitry.
While the 82559 is in the D0, D1, or D2 power state, it is initialized by the RST# level. When the
82559 is in the D3 power state, the system bus may be in the B3 bus power state. In the B3 power
state, the PCI RST# signal is undefined; however, the auxiliary power source proposal for the PCI
Specification, Revision 2.2 is for the PCI RST# signal to be an active low. Therefore, the 82559
uses the PCI RST# similarly to the ISOLATE# signal in D3 power state. Following the trailing
edge of the PCI RST#, the 82559 is initialized while preserving the PME# signal and its context.
Note:
According to the PCI specification, during the B3 state, the RST# signal is undefined.
The transition from the B3 power state to the B0 power state occurs on the trailing edge of the
RST# signal.
The initialization signal is generated internally in the following cases:
Active RST# signal while the 82559 is the D0, D1, or D2 power state
RST# trailing edge while the 82559 is in the D3 power state
ISOLATE# trailing edge
Figure 9. Isolate Signal Behavior to PCI Power Good Signal
PCI power good signal
Required ISOLATE#
signal behavior
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