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參數(shù)資料
| 型號： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 54/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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82559 — Networking Silicon
44
Datasheet
The PHY unit auto-select function determines the operation speed of the media based on the link
integrity pulses it receives. If no Fast Link Pulses (FLPs) are detected and Normal Link Pulses
(NLPs) are detected, the PHY unit defaults to 10 Mbps operation. If the PHY unit detects a speed
change, it dynamically changes its transmit clock and receive clock frequencies to the appropriate
value. This change takes a maximum of five milliseconds.
5.2
10BASE-T Functionality
5.2.1
10BASE-T Transmit Clock Generation
The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz
crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal
MAC at 2.5 MHz.
5.2.2
10BASE-T Transmit Blocks
5.2.2.1
10BASE-T Manchester Encoder
After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock
performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the
value is 1b then the transition is from low to high. If the value is 0b then the transition is from high
to low. The boundary transition occurs only when the data changes from bit to bit. For example, if
the value is 10b, then the change is from high to low; if 01b, then the change is from low to high.
5.2.2.2
10BASE-T Driver and Filter
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. This allows the two technologies to share the same magnetics. The PHY unit
supports both technologies through one pair of TD pins and by externally sharing the same
magnetics.
In 10 Mbps mode, the PHY unit begins transmitting the serial Manchester bit stream within 3 bit
times (300 nanoseconds) after the MAC asserts TXEN. In 10 Mbps mode the line drivers use a pre-
distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the
second half of “wide” (100ns) Manchester pulses and maintain a full drive level during all narrow
(50ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide
pulses, a major source of jitter.
5.2.3
10BASE-T Receive Blocks
5.2.3.1
10BASE-T Manchester Decoder
The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The
Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and
Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/
nibble. The high-performance circuitry of the PHY unit exceeds the IEEE 802.3 jitter
requirements.
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