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參數(shù)資料
| 型號： | 82559 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Fast Ethernet Multifunction PCI/CARD bus controller(快速以太網(wǎng)多功能PCI/CARD 總線控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, BGA-196 |
| 文件頁數(shù)： | 47/124頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | 82559 |
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Networking Silicon — 82559
Datasheet
37
4.8.1
Full Duplex
When operating in full duplex mode the 82559 can transmit and receive frames simultaneously.
Transmission starts regardless of the state of the internal receive path. Reception starts when the
internal PHY detects a valid frame on the receive differential pair of the PHY.
The 82559 operates in either half duplex mode or full duplex mode. For proper operation, both the
82559 CSMA/CD module and the PHY unit must be set to the same duplex mode. The CSMA
duplex mode is set by the 82559 Configure command or forced by automatically tracking the mode
in the PHY unit.
The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by
setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the
internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the
duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto-
Negotiation.
The selection of duplex operation (full or half) and flow control is done in two levels: MAC and
PHY. The MAC duplex selection is done only through CSMA configuration mechanism (in other
words, the Configure command from software).
4.8.2
Flow Control
The 82559 supports IEEE 802.3x frame based flow control frames only in both full duplex and half
duplex switched environments. The 82559 flow control feature is not intended to be used in shared
media environments.
Flow control is optional in full duplex mode and can be selected through software configuration.
There are three modes of flow control that can be selected: frame based transmit flow control,
frame based receive flow control, and none.
The PHY unit’s duplex and flow control enable can be selected using NWay* Auto-Negotiation
algorithm or through the Management Data Interface.
4.8.3
Address Filtering Modifications
The 82559 can be configured to ignore one bit when checking for its Individual Address (IA) on
incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least
significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority
indication bit. When configured to do so, the 82559 passes any frame that matches all other 47
address bits of its IA, regardless of the U/L bit value.
This configuration only affects the 82559 specific IA and not multicast, multi-IA or broadcast
address filtering. The 82559 does not attribute any priority to frames with this bit set, it simply
passes them to memory regardless of this bit.
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